Shaping the yield curve

Integrated circuit designs are becoming ever more complex, with more analogue and digital functions fitted into a single chip and ever higher clock frequencies, all of which can hit the yield of the chip in production. To make matters worse, the coming 90nm and 65nm processes mean that design rules are becoming harder to meet, and mask costs are spiraling. The finer geometries also lead to greater problems with signal integrity and yield, and conspire to make it hard to deliver correctly functioning chips with good yield and area in time for the target market.

At the same time the design time is reducing, and there is less time to tweak the design to get the best possible yield. Designers of commodity devices will trade off many revisions of a mask set, costing millions of dollars, just to get a one percentage point increase in yield.

One way around the problem is to use larger design margins and leave more space than strictly necessary to make sure that the chip yields effectively. But this is an expensive option, leaving the chip significantly larger than necessary.

Minimizing the time to yield requires getting the design right as quickly as possible within the right constraints. This does not necessarily mean just making the design tools run as fast as possible. It is more important that iterations are reduced, and the number of cycles of transferring data from one tool to another in each iteration is also reduced. This means integrating many capabilities into one tool, and makes checking of all the rules pervasive throughout the tool vital, so that designs are increasingly correct as they go forward through the flow, and iterations are reduced or eliminated.

Changes to the routing technique during the design process can dramatically improve the time to yield while keeping the chip as small and cost effective as possible.

Routing algorithms

The vast majority of routing tools are built around grid-based algorithms. These take a complete design and break it up into a grid of small squares in a database, blocking out areas of the grid where components prevent wires being routed. Wires are then routed on along the grid-lines to link up components in the design, using the number of squares in the grid to determine the minimum path for the routing.

Fully and properly representing all the design data required is hugely memory intensive, so the majority of the design data – what the components are, how the wires interact – is dropped from the routing database. Although this technique allows for very rapid routing, it suffers from two main problems. Firstly, controlling the interactions between different classes of wires (eg analogue and digital) or managing signal integrity issues, is difficult. Secondly, the grid may force the wires to be at a non-optimal pitch due to the requirement to via between layers where they have common grid points. This can lead to an inefficient layout, leaving space for vias even in areas where no vias are needed, and also the rigid grid makes it costly to increase the spacing between wires to solve signal integrity issues.

Shape-based routing

The idea of shape-based routing has been around for many years in board design, but its strengths in area efficiency, signal integrity and yield improvement, particularly in analogue and mixed signal designs, are driving its use for chip design.

Shape-based routing does not use an abstract grid, but creates a ‘flood' in one direction until it reaches an obstruction (fig 1). It then finds an unobstructed ‘edge' in the direction of the target and floods in that direction until it reaches another obstruction, and the process repeats until it reaches the target.

Figure 1: Using a shape-based routing algorithm to determine the route between two points.

Each edge is assessed, or ‘costed' for the distance it takes, but also for other factors such as parasitics, and this gives the technique significantly more flexibility. All the costs are kept throughout the run, as one direction of exploration may end up in a dead end or in a high cost route, while another previously unfavoured edge further back may result in a lower cost route overall. The technique is also coupled with ‘rip up and re-try', where the cost of taking a path that causes an error is also included in the calculation.

Figure 2: The routing uses the full design data, allowing interactive signal analysis

This allows a wide range of data to be used while the design is being routed, comparing a route against design rules and constraints to get the most efficient routing the first time around, rather than going through the many iterative cycles of routing and post-processing that is necessary with the grid-based approach.

The ‘push aside' technique allows the routing algorithm to identify areas where it may be able to pass by moving an existing wire out of the way, rather than going a long way around or creating an error. This gives shorter wires with less vias, and overall a higher efficiency of routing, which means some designs can be routed this way which are impossible using a grid-based approach.

Designer directed routing

Shape-based routing is also interactive and iterative. If something is obviously wrong, the designer can stop the automatic routing and make an adjustment to the floorplan, the routing costs or other rules, or even route a particular section by hand, and then continue with the auto-routing.

This approach also allows the tool to spread tracks apart to reduce capacitance, make tracks wider to reduce the resistance, both helping to reduce the RC delays. As these steps happen during the routing process, rather than afterwards in a separate tool, the process is quick and helps designs to be correct without iteration.

The shape-based approach works normally at the manufacturing resolution of the reticles used in masks, rather than at a coarse wire pitch. Having a tighter resolution allows more of the chip area to be used effectively, within the constraints of the design rules and signal integrity analysis, and moving to such resolution in a grid-based tool dramatically increases the memory requirement and run-time of the tool.

Analyzing parasitics

As all the design data is available during the routing process, the parasitics are part of the ‘cost' analysis and tied into the design rule checking tools directly, so the routed path meets the design requirements from the first attempt. Even when tracks are pushed aside to make room for new tracks, that change is incorporated into the routing process and new decisions in the auto-router take this into account because it is using the underlying design database.

That is not to say that post-layout analysis tools and iterations are not necessary, but these are used primarily to check the results, rather than to make changes that cause new iterations.

Design for Manufacture (DFM) rules can also be integrated into the router, adding 'tidying' and 'smoothing', which remove ugly and redundant wiring patterns, reducing the number and length of routing segments and the number of vias, and increasing the spacing between the tracks. The yield risks in the design, such as tightly spaced tracks and single-cut vias, can also be analysed during routing, and the tracks automatically pushed apart to create better yielding devices

Another DFM concern is metal density. Both etching and planarization processes used in manufacturing require an even density of metal to be left across the chip, even if there is no wiring some areas of the design. Pulsic's Lyric tool balances the metal density by adding patches of metal in sparse areas of the chip and making ‘slots' in existing wide tracks such as power and ground lines.

Engineering Change Orders (ECOs)

The incremental capability is a key advantage in reducing the time taken to incorporate ECOs. If devices have to be added, or removed, this can be done locally, pushing tracks aside and re-routing them without having to re-route large areas of the design. This means that changes have only local consequences and so it is likely that the process will converge rapidly.

Memory Design

One of the areas really taking advantage of shape-based routing is memory design, as Pulsic's shape-based technology is applicable to designs with extreme aspect ratio cell areas (often 30 times as wide as they are high), with limited numbers of routing layers (normally 2 or 3), and where a large fraction of the signals having to travel for a significant distance. This makes it good for DRAMs, SRAMs, FLASH and imaging sensors.

Conclusion

Tackling the challenges of signal integrity and design-for-manufacture in mixed signal and high speed designs is a key issue in the design industry. Using an innovative algorithm such as shape-based routing allows designers to have more control of the routing process while it is happening, converging on the best solution for their design style significantly more quickly than grid-based routing will allow.