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News Article

THE ‘X’ FACTOR — A new angle on DFM and DFY

Over the past two years, a tsunami called design for manufacturing (DFM) has engulfed the semiconductor industry. Anyone attending the most recent Design Automation Conference (DAC) couldn't avoid DFM in booths, papers, panels and presentations. And who would have thought we'd see Applied Materials at DAC and Synopsys at Semicon West last July, talking about the same subject? Ken Rygler, CTO and President of Rygler and Associates discusses.
According to some, the principles of DFM date back to the Renaissance, although the term did not enter widespread usage until the mid-1980s. Yet, it is only in the past two years that DFM has surfaced in the semiconductor industry, arguably employing some of the most complex design and manufacturing on the planet. Why now?

• The 130nm production ramp was slow, arduous, and costly. Some blamed the introduction of copper and low K dielectrics, others the disastrous semiconductor downturn. Still others, including this writer, the lack of manufacturability of the 130nm designs.
• The disaggregation of the semiconductor supply chain, culminating in the cleavage of semiconductor design and manufacturing itself.
• The extension of optical lithography deep into the sub-wavelength (SWL) realm, ending the WYSIWYG era forever. Printed silicon patterns resembled impressionistic art more than the elegant rectilinear forms their creators laid out.

But, what is DFM, as it relates to the semiconductor industry? Mark Rencher, CEO of Pivotal Enterprises, has authored an extensive series of DFM articles. He offers the following definition of DFM, as contrasted with Design for Yield (DFY): "DFY is the management of the design's sensitivity to the manufacturing process, while DFM is the management of technology constraints (rules, lithography) applied to a design. For example, design rule checks define the minimum wire spacing (pitch) but do not mention anything about relaxing the spacing to avoid particle defect shorts. A common example of DFY in practice is to evaluate an analog circuit's sensitivity to process variation."

While DFM has a long and proud history (dating back decades or centuries, depending on your perspective), it seems more appropriate for assembly, where the emphasis is on reducing labor costs and improving throughput. If we accept Rencher's definition, the semiconductor industry's focus should be on DFY. Companies which own $3 billion wafer fabs operating at low yields will not be in business very long. Time to market demands, particularly in the consumer market, reward the first company which can fill the pipeline with high volume, high performance devices. Skyrocketing design and photomask costs continue to reduce the new designs: semiconductor companies must make bigger bets on fewer products. Finally, feature-driven yield has superceded defect-driven yield as reflected in Figure 1.
The challenge of successfully integrating silicon design and manufacturing has intensified as we entered the deep sub-wavelength era. Despite the significant growth in the number of design rules attempting to codify manufacturing constraints, the 130nm ramp proved extraordinarily painful for most companies. With features being printed at half or a third wavelength, more design rules simply weren't sufficient: deep SWL lithography means a change in design philosophy as lithographers continue to implement aggressive resolution enhancement technologies (RETs) like optical proximity correction, strong phase shift masks, and off-axis illumination. Design tools that fully comprehend the effects of deep SWL lithography, the explosion in RETs, the unchartered effects of immersion lithography and the unique requirements of the maskmaker, remain in the future. The ability to continue lithographically scaling a generation every two years is now seriously in question. Unable to fully rely on scaling, new technologies are required to achieve the performance and cost benefits associated with Moore's Law.

With scaling becoming more costly and less reliable, a number of new approaches have emerged to enable the continuation of "smaller, faster, cheaper." These include such "new" ("new" because I have observed what Paolo Gargini told me years ago—that most "new" technologies require about a 30 year incubation period) materials like SiGe, new technologies like strained silicon and SOI, new architectures like "X Architecture", a revolutionary embodiment of Pythagorean theory, and new levels of collaboration.

Of these, the X Architecture bears additional analysis, as it has helped blaze a trail for design for yield by providing a model of collaboration essential for the effective integration of silicon design and manufacturing. X was innovative at several levels, not the least of which was its ability to provide a unique approach to "smaller, faster, cheaper" and higher yields. The X Architecture enables shorter and more direct interconnects, reducing wire length and significantly reducing the number of vias.

The X Architecture—Right Solution, Right Time
In the mid-1980s, channel routers gave way to area routers, which enabled over-the-cell routing and the sea-of-gates architecture that fueled the ASIC design explosion of the late 1980s and early 1990s. These technologies were developed based on the assumptions and methods dictated by the computing power available at that time. Computing technology has since improved by three orders of magnitude, however, presenting an opportunity to conceive an entirely new approach to physical design.

Based on new algorithms that leverage the power of today's sophisticated computing resources, the X Architecture targets chips with five or more metal layers. With this new design scheme, the primary direction of the interconnect in the fourth and fifth metal layers is rotated by 45 degrees in relation to the conventional orthogonal, or "Manhattan," architecture. Unlike Manhattan-based routing, X Architecture designs include routing in any of eight directions—allowing more direct connection between any two transistors on a chip. Figure 2 illustrates the 45-degree angles employed in designs created using the X Architecture. In addition to these large-scale diagonals, each layer can have small-scale diagonals. It is the combination of both that creates the reduction in interconnect observed in chips implemented using the X Architecture.
The promise of the X Architecture is that by employing diagonal routing in a pervasive manner, designers can reduce wire length up to 20 percent and vias up to 30 percent—significantly improving chip speed, power, cost, and time to market as well as enhancing signal integrity and reliability, and increasing not only the probability of a successful first silicon, but the manufacturing yield as well.

The implications of the X Architecture for improving design manufacturability are clear, as are the complexities associated with implementing this approach throughout the industry. Thus, a new degree of cooperation and collaboration is required between suppliers up and down the design-to-silicon chain to ensure manufacturability and economic viability. This is a lesson learned from the efforts to commercialize a number of process and material advancements (e.g., low-k dielectrics, SOI) whose adoption would likely have spread faster through broader collaboration.

The X Initiative—formed to support and drive proliferation of the X Architecture throughout the semiconductor industry—has brought together companies from every segment of the semiconductor supply chain to jointly address design for manufacturing issues using the X Architecture as the common platform. In the process, the basis for improved yields was found as well.

The greatest issues with any new chip technology include the availability of required design and verification tools; photomask production and costs; the management of data requirements and data volume through the supply chain; and its impact on yield. To address these concerns for the X Architecture, the X Initiative is focused on educating the supply chain about the architecture, accelerating fabrication of X Architecture chips, and tracking and promoting the technology's commercial proliferation. The X Initiative is thus focused on advancing the usage of the X Architecture by ensuring its support throughout the design and manufacturing cycle.

In the three short years since the inception of the X Initiative, a large number of significant milestones have been achieved through cooperative work between X Initiative members. The fabrication of the first X photomasks in the late 2001 and early 2002 by DuPont Photomasks and Dai Nippon Printing were followed by successful lithography demonstrations at 130nm by ASML and Nikon during 2002, 90nm test chip fabrication in 2003, and 65nm in 2004 by Applied Materials. A parallel effort in design produced the first functional chip design by Toshiba in early 2003, culminating in the introduction of the first commercial SoC built by Toshiba in 2004.

The cumulative result of these and other ongoing collaborations is that the manufacturability of this new design paradigm has been established early in its development cycle—preparing the entire supply chain to design and manufacture these new chips. The findings show a clear and logical progression of the X Initiative members' work.

Of particular note is the succession of projects illustrating the manufacturability of the X Architecture at progressively smaller process-technology nodes. X Initiative members in the design to manufacturing supply chain have shown through a collaborative effort that the X Architecture is manufacturable at the 180-nm, 130-nm, 90-nm and 65-nm technology nodes using existing production equipment.

The collaborative work showed that the current generation of layout tools, mask tooling, and wafer processing can be used to manufacture X Architecture layout with the same level of linewidth control and comparable electrical characteristics as conventional Manhattan layout at the 90-nm technology node. The ability to use the same manufacturing flow for the X Architecture as that used for Manhattan layout demonstrates its integration worthiness and economic viability. The demonstration of CD uniformity and electrical integrity at a 212-nm pitch is a good indicator that the X Architecture is scalable to the global wiring level of the 45-nm technology node, and is a viable, long-term strategy for the design community.

Most recently, PDF Solutions conducted a simulation study comparing the yield benefits of traditional Manhattan designs vs. the X Architecture at the 130-nm process node. This yield analysis study demonstrated that the X Architecture could improve yield and good die per wafer by 16 percent and 15 percent, respectively, for 200- and 300-mm wafers. This study also validated via and die-size reductions, as well as critical area shorts when implementing the X routing technology. The X Architecture not only provides another vehicle to achieving "smaller, faster, cheaper", but has also provided a model for a DFY infrastructure. Clearly, effective supply chain collaboration can produce superior results.

Moore's Law can continue to provide the engine to drive the electronics industry to another $1 trillion in growth. Whether or not this materializes over the next one to two decades will depend, in large part, on economics, not technology. Scaling and larger wafers have been the principal drivers for "smaller, faster, cheaper" and the low hanging fruit is pretty well tapped out. Collaboration across the entire supply chain targeted at yield improvement and time to market must become more than a marketing slogan but a way of life. The lessons from the 130nm ramp were painful: $2 billion wafer fabs cannot ramp new technology for years at low yields. Designers and design tool providers must begin to take some ownership of device yields. Collaboration, yield, and time to money—not technology—will separate the winners from the losers. DFY or die.
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