Reliably testing beyond 90nm

In keeping with Moore's law, shrinking geometries are driving the development of new materials, processes, and structures. In turn, these developments force new requirements on electrical parametric measurement. With respect to reliability, ultra thin gate dielectric development has drastically changed the test system architecture and practices needed to characterise device lifetimes. More specifically, traditional systems fall short in several areas including overall system throughput, measurement speed, and measurement buffer depth. For instance, the bias temperature instability (BTI) wear out mechanism characterisation requires not only precise control of stress voltage and duration, but also very fast transitions between sourcing a stress condition and measuring degradation as well as minimising the time that the test structure is not undergoing stress. To meet these timing requirements and create very large statistical measurement samples for meaningful analysis, parallel testing is required.

Development and adoption of ultra thin gate and high-K dielectrics are driving concerns about reduced device lifetimes due to new degradation mechanisms. These mechanisms include negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and progressive breakdown during time dependent dielectric breakdown (TDDB.) Understanding and characterising the effect of these mechanisms on device lifetimes requires new test methodologies.

NBTI / PBTI – negative or positive bias temperature instability is responsible for shifts in Vth, increases in sub threshold drain current, reduced drive currents, and overall slower device operation when the CMOS transistor is subjected to elevated temperatures and gate bias voltages. It is generally accepted that BTI is caused by charge traps developing when hydrogen species are liberated from the dielectric interface. These hydrogen species can find their back and anneal, neutralising the degradation when the voltage and temperature stress is removed. It is the rate of annealing that makes meaningful BTI measurements difficult. Experimental results show that annealing, and the consequential degradation recovery, begins immediately after the stress is removed. The key to meaningful BTI characterisation is to measure the degradation as soon as the gate stress voltage is removed.

TDDB – Time dependent dielectric breakdown has evolved to address many different breakdown behaviours. Thick silicon oxides, consistent with older technology nodes, display hard breakdown, which is easy to identify by the increase in leakage current on the order of several magnitudes. With the development of more advanced technology nodes, the thinner silicon oxides display soft breakdown which is characterised by an abrupt increase in the leakage current noise sometimes accompanied by a slight increase in leakage current and is area dependent. High-K dielectric breakdown is sometimes characterised by progressive breakdown, which is characterised by a progressive increase in leakage current and leakage current noise and is area independent. The key to meaningful TDDB characterisation is to independently measure the leakage current on each test structure at a rate of 100s of sample per second.

Statistical Challenges – During the development of a new technology node or modification to a process, or during process qualification, attaining a statistically significant sample of device lifetime performance is critical. The sooner a statistically significant sample can be analysed, the sooner the risk is reduced or managed. New BTI and TDDB testing require that each test structure is stressed and characterised by dedicated stress-measure circuitry. Conventional systems can accommodate this requirement by limiting the number of structures under test at one time.

Test System Requirements
Conventional semiconductor parametric analysis wafer level reliability (WLR) and package level reliability (PLR) test systems incorporate a few SMUs (source measure/monitor units) and a large switch matrix. Most conventional reliability test methodologies provide for relatively slow characterisation and monitoring of test structures. As a result, test structures are typically "gang" stressed, "gang" monitored, and sequentially characterised. In a "gang" stress/monitor architecture, the switch matrix connects one or two SMUs to a number of devices in parallel. The SMUs provide a programmed stress voltage while monitoring the gang leakage current. Between stress cycles, the devices are characterised sequentially by multiplexing each device to SMUs that perform a set of I/V curves that allow extraction of critical parameters.

While conventional systems provide a good economical solution for older reliability tests, they fall short for BTI and TDDB testing for 90nm and more advanced technology nodes. The temporal dynamics of new ultra thin silicon dioxide and high-K dielectric require high speed monitoring and characterisation to make meaningful degradation measurements. Specifically, BTI and TDDB demand dedicated independent SMU per device architecture in which each device (test structure) is assigned dedicated SMUs for the duration of the reliability test. While conventional systems can support this requirement, they are only able to test 2 or 3 devices at one time. As a consequence, conventional systems require very long periods of time to accrue the large statistical sample required for significant analysis.
A system that is optimised for BTI and TDDB testing consists of a large array of SMUs to allow SMU per device testing at high speeds. Additionally, each of these SMUs must be capable of making high speed measurements and provide a deep measurement buffer to ensure that breakdown events are captured.

System Realisation
Semiconductor reliability test systems – whether used for technology development, process integration, or process qualification and monitoring – must be able to accommodate a wide range of both device characterisation (parametric analysis) and reliability testing. To meet these two goals, a system must be capable of both high resolution sensitive measurements and high speed parallel measurement. By integrating a large array of high speed parallel SMUs with a more conventional parametric test system, a nearly ideal solution can be realised. A conventional parametric test system composed of a few high resolution sensitive SMUs and a low-leakage switch matrix provides for high voltage, low current, and very sensitive measurements. The high speed parallel channels are integrated via a "bypass switch" as shown in figure 1.

The bypass switch allows either the use of the high resolution channels or the high speed parallel channels without interfering with low leakage signal paths.

Anatomy of a High Speed SMU
In the simplest terms, a high speed SMU must be able to autonomously conduct a sequence of source-measure steps unimpaired by shared resources and system limitations. There are additional requirements that make a high speed SMU more suitable for semiconductor lifetime testing. These include:

• Seamless transitions between stress mode and measurement mode – Key to good high speed NBTI and TDDB degradation measurements is the seamless transition between the stress voltage, the degradation measurement condition or sweep. This transition must be nearly instantaneous and cannot "pass through zero" as with a shared SMU system.

• High speed high resolution A/D with programmable integration aperture – Measuring NBTI degradation requires precisely timed and fast measurements. While the fastest measurement (or shortest integration aperture) might be best, there is always a trade-off between speed and resolution. The longer the integration aperture, the better the overall signal to noise ratio of the measurement. Providing a programmable integration rate allows the reliability engineer to make the best compromise between speed and accuracy.

• Deep measurement buffer – TDDB for high-K testing often requires that measurements be made every few milliseconds for several minutes requiring the SMU to store many tens of thousands of measurements locally. Too shallow a buffer requires the test execute software to intervene during the degradation measurement to prevent data from being overwritten. This intervention will slow the overall measurement rate significantly. To enable fully autonomous operation, a high speed SMU must have a deep measurement buffer that can store more than 100,000 measurements locally. The test executive software can then transfer the data during the stress cycle rather than interrupting the measurement sequence.

• High density and low cost – To generate the large statistical samples of lifetime data, a large number of test structures must be characterised. The only way to accelerate the process is with a large number of SMUs. Two practical implications are that the size and cost of the high speed SMU must be constrained. By constraining the high speed SMU source and measure ranges to those that are required for NBTI and TDDB, the size and cost can be significantly reduced.

• Channel synchronisation – To ease the complexity of the system software, it is critical that all of the high speed SMUs execute synchronously. The use of synchronous high speed SMUs means that the system software is tasked only with managing and monitoring the on-stress and off-stress time of the group of high speed SMUs rather than trying to track each SMU independently.

Figure 1. The bypass switch makes it easy to combine high speed parallel channels with high resolution channels in a single, highly flexible system.

Figure 2. S510 can be configured for 20 to 72 high speed parallel channels.