News Article
Innovative ADC breaks through power barriers
IMEC’s 90nm RF CMOS program has designed a 4-bit, 1.25Gsamples/s, 2.5mW high-bandwidth ADC prototype, which has achieved a world-record figure of merit of 0.16pJ/conversion step.
IMEC’s 90nm RF CMOS program has designed a 4-bit, 1.25Gsamples/s, 2.5mW high-bandwidth ADC prototype, which has achieved a world-record figure of merit of 0.16pJ/conversion step. The circuit has been processed in IMEC’s 90nm RF CMOS prototype manufacturing technology, which features an effective oxide thickness of 1.5nm and physical gate length of 70nm. The NMOS cutoff frequency ft is 170GHz. The maximum oscillation frequency fmax is 240GHz. The NMOS and PMOS threshold voltage matching coefficients are respectively 4.0 and 3.0 mV µm.
To reduce the power consumption, all the non-essential blocks (track-and-hold, preamplifiers, reference ladder and bubble error correction) of the flash architecture have been removed. First, 15 comparators sample the data and amplify it. The output comparator outputs are stored in 15 set-reset latches. The stored thermometer code is then converted into a 4-bit gray code by the ROM-based encoder which has intrinsic error correction properties.
The implemented comparator circuit combines the sampling, amplifying and reference levels functions with high accuracy and high sampling speed at low power. The reference levels are generated by an intentional imbalance that is introduced in the input differential pair. The threshold voltages are then calibrated with DC input signals and are sufficiently accurate to reduce the integral non-linearity to less than 0.15 LSB.
To reduce the power consumption, all the non-essential blocks (track-and-hold, preamplifiers, reference ladder and bubble error correction) of the flash architecture have been removed. First, 15 comparators sample the data and amplify it. The output comparator outputs are stored in 15 set-reset latches. The stored thermometer code is then converted into a 4-bit gray code by the ROM-based encoder which has intrinsic error correction properties.
The implemented comparator circuit combines the sampling, amplifying and reference levels functions with high accuracy and high sampling speed at low power. The reference levels are generated by an intentional imbalance that is introduced in the input differential pair. The threshold voltages are then calibrated with DC input signals and are sufficiently accurate to reduce the integral non-linearity to less than 0.15 LSB.
