Seeking future engineering
IEDM is the prime conference for semiconductor devices, and the place where the chip companies like to strut their technology. It alternates between San Francisco and Washington – this year was Washington's turn.
The weather there in early December is a bit unpredictable. This year it was cool and clear to start, but then a belt of snow came through, dropping two inches or so. Of course that just about shut things down, but it was picturesque for a short while. Other years it's been balmy, with temperatures in the 70s and the locals sunning themselves at café patios.
This year attendance was up from the typical 15-1600 to almost 1800. Usually in Washington it is lower than at the alternate venue in downtown San Francisco, which last year was about 2300. This felt like industry optimism, the mood of the attendees was pretty upbeat. In all there were a total of 251 papers delivered in 41 sessions in the three days.
Chipworks does reverse engineering of the latest semiconductor devices, so my purpose in attending is to see what technology is likely to come on stream in the next year or so. Consequently, I tend to take in the papers from chip manufacturers, and miss out on the more academic or farther-out topics, even though there's bound to be some really interesting stuff there.
Sunday
Short course day – Low Power SoC CMOS Technology in my case – pretty good, overall, with a potted summary of process techniques to start by Scott Crowder of IBM, then embedded memory by Yasushi Yamagata of NEC in the morning.
In the afternoon we had the circuit perspective – how design can reduce power demands by Shekhar Borkhar (Intel), and analog/RF from Willy Sansen from KU-Leuven. The latter was way over my head with details of analog circuits in nanometer technologies, but Willy was an entertaining speaker and he covered a lot of ground. The bottom line was that 65-nm technology takes transistor operating frequencies into the gigaHertz range – so finally, RF can be integrated into silicon, instead of having to use high-mobility III-V materials or SiGe. That will have some interesting industry consequences in the next few years, I'm sure..
The day finished with Freescale's Colin McAndrew covering off the modelling aspects of analogue, mixed signal, and RF design; again, over my head, but showing that models are keeping up with the technology.
Monday
The conference always starts with awards ceremonies, and then a morning of invited papers presented in a common session. This year we had papers on MEMS from Benedetto Vigna of ST, power scaling from Mark Horowitz of Stanford, and display technology from Kouji Suzuki of SED Inc, which appears to be a silicon emission display spin-off from Toshiba. All were competent reviews of their topics, but after sitting for three hours without a break, a stretch was definitely needed!
The afternoon had eight parallel sessions, so it's impossible to sit in on all of them – one of the downsides of IEDM! I concentrated on the Advanced CMOS papers, which were mostly 65-nm processes from the IDMs, although the kick-off paper was a lithography review from TSMC. If 90-nm was the node that launched strain engineering, then 65-nm is the node where it is ubiquitous, and in a few different flavours. There is memorised stress, SiGe stress, compressive and tensile nitride stress, uni-axial and biaxial stress – quite a strain thinking about it, really (couldn't resist that!).
Intel and the AMD/IBM/Toshiba consortium had 65-nm processes using multiple stressors (AMD etc on SOI, Intel on bulk, papers 3.3 and 3.4). The IBM/Chartered/Infineon coalition announced a low-power 65-nm process on bulk silicon using no strain, but PMOS enhancement using "substrate modification", which I take to mean wafer rotation by 45o to give a <100> direction to the channel (paper 3.5).
A couple of the low power papers, titled as "65-nm", actually had gate dimensions and metal-1 dimensions more in line with the ITRS 90-nm node. These are good examples of why the ITRS organization is trying to get away from the tyranny of node dimensions, and work with process generations – if you can get away from the hang-up about numbers, these processes are traditional 30% shrinks of their 90-nm equivalents.
Other sessions covered off high-k dielectrics, interconnect, displays and flexible electronics, mobility enhancement (more strain), non-volatile memories, reliability, and modelling.
Tuesday
Seven sessions today, morning and afternoon; the most popular was High Performance CMOS, rather than Advanced CMOS; the emphasis was 45-nm and fully-silicided gate (FUSI) processes, with papers by Intel, TI, Toshiba, Fujitsu, IBM, and AMD.
For me the most important paper was IBM/AMD/Toshiba's integration of multiple stress techniques into SOI processes (paper 10.5). It looks as though we can look forward to seeing tensile and memorized stress on NMOS, and compressive nitride and embedded SiGe stress on PMOS; it appears that these can all be additive, although there is some penalty in external resistance. AMD claim a 40% speed increase over the un-stressed equivalent in their Athlon product.
IBM have been looking at RF in CMOS, and demonstrated an fT of 330 GHz in their 65-nm SOI process (10.7). This was taken on a 27-nm transistor, which is probably a bit on the small side for a production 65-nm process, but it shows that CMOS processing is now getting into the area where low-power applications such as wireless USB can be fully integrated into silicon. This was corroborated in more detail in a MIT/IBM paper in session 15 (15.3).
In the DRAM/Flash session, Samsung showed an evolution of their recessed (trench) transistor DRAM cell, in which they have rotated the wafer by 45o, to orient the horizontal component of the channel in the <100> direction, instead of the normal <110>. This makes the channel orientation uniform, since the trench sidewalls also have <100> direction, and improves transistor current drivability. It should make the gate oxide growth more uniform too, and improve PMOS drive current, since hole mobility is ~9% higher in the <100> direction.
In the afternoon my main focus was the session on strained silicon – definitely a major focus of the meeting, given its ubiquity in the advanced process papers. The IBM/Chartered/Samsung bulk silicon coalition has been looking at embedded SiGe source/drains + laser anneal (20.1), and claim defect-free SiGe in bulk silicon substrates for the first time, and improved PFET performance.
Sony/Toshiba took a different tack by looking at a strained-silicon on SiGe substrate (i.e. bi-axially strained) with rotated <100> channel and epi-Si source/drains, and tensile nitride (20.4). This gave them 15% NMOS and 25% performance improvement compared with the <110> channel bulk silicon equivalent.
The IBM/AMD/Sony(Toshiba) SOI alliance tried memorized stress and dual-stress liner (DSL) on fully-depleted devices on ultra-thin SOI, with raised source/drains (RSD) to reduce contact resistance (20.5). The DSL technique was announced at last year's IEDM, and uses compressively-stressed nitride to enhance PMOS performance, and tensile nitride to enhance NMOS performance. The trade-off here is the reduced contact resistance with increased RSD height, but which reduces the stress applied by the liner nitride.
In this paper the SOI thickness was 18 nm and RSD height 38 nm. The NMOS performance was improved by both the memorized stress and liner stress, and PMOS saw improvement from the liner stress, without degradation from the stress memorization process. Fully-depleted devices and ultra-thin SOI are somewhat in the future, but this paper shows that the stress techniques can be used when we get there.
The compound semi session had some interesting papers on gallium nitride devices, but the one that caught my eye was a GaN-on-silicon FET from Nitronex (23.1). Most GaN transistors are produced using silicon carbide substrates, so a silicon-based high power FET giving >350 W should be of interest for base-station use. Nitronex are currently targeting the WiMAX market with a family of GaN-on-silicon devices in the 10 – 50 W range.
Other morning sessions were on nanotubes and nanowires, MEMS, compound semi and power devices, dielectric breakdown, and advanced integration (i.e. papers that didn't fit in other sessions). In the afternoon there was more on nanotubes and nanowires, also high-k dielectrics, flexible electronics, novel devices, and electrical degradation.
After the afternoon sessions we enjoyed some Applied Materials hospitality at a symposium on "The Scaling Dilemma" hosted by Scott Thompson of the University of Florida. Applied had rounded up some leading lights from IBM, Intel, TI, ST, and TSMC, together with their own Mark Pinto. Each made a short presentation on their perspective of what the next couple of process generations will look like, and then Scott put some prepared questions to each panelist.
The consensus, at least as I interpreted it, was that high-k dielectrics may make into 45-nm, but nobody's betting on it; gate shrinking will continue, aided by immersion lithography (at least at TSMC); strain will be extended and enhanced; and oxide dielectrics are stuck at 12 -15 Angstroms.
Tom Bonifield, TI's interconnect integration manager, commented that there will be more metal levels and lower-k dielectrics, but basically an evolution of the changes from 90 – 60-nm. Work is ongoing on improving line conductivity, but more metal levels and design ingenuity will have to take up where process techniques are limited.
Ghavam Shahidi created some discussion when it came to the following generations – he stated that FinFETs and other multiple-gate structures will "never happen" because of the difficulties making them manufacturable in chips that will have billions of transistors. Tom Skotnicki of ST disagreed, but it appeared that he was thinking of dual-gate planar structures, which should be easier to integrate.
There was a question about the timing of 450-mm wafers, which caused much eye-rolling from all, but Mark Pinto fielded it and made the point that if and when they come, there needs to be a better return for the equipment industry than that from the 300-mm rollout.
The regular evening panel sessions were quite well attended, but they seemed to have the usual artificial atmosphere. People come because they don't want to miss anything, but the topics, while relevant, are not always gripping. This time we had discussions about the future of industry R&D (will it price the business out of existence?), and whether non-volatile memory will scale past 2010. In both cases the debates ended with the rather unsurprising conclusions that R&D and the industry will still be around, and so will current-style NVM. After all, the new decade is only four years away!
Probably the best comment of the day (and maybe of the conference) came from T.P. Ma from Yale. T.P. is one of the conference regulars, and has spent a good chunk of his career working on CMOS gate dielectrics. This year he was presented with the Andy Grove award at the IEDM lunch, and his first comment in his short acceptance speech was "High-k dielectrics are in a mess!" Will we see high-k in chips soon? I doubt it!
Wednesday
Another full day – most of the morning in the image sensor session.
Sony are trying to improve pixel sensitivity by replacing shallow trench isolation (STI) with a surface oxide and a channel-stop implant (33.1). This allows the photodiode area to be expanded within the pixel without the increased dark current caused by interaction with the STI edge. They claim that using this technique they can get the same performance from a 1.7 µm pitch pixel that they previously achieved with a 3.0 µm pitch.
Samsung continue to push their pixel size down, with a 1.9 x 1.9 µm2 pixel using a four-shared pixel architecture in a 130-nm process (33.2). Noise was reduced by modifying the anneal cycles and going to a plasma nitrided gate oxide.
Albert Theuwissen of DALSA gave an interesting couple of talks (33.3 and 33.6); the first about the role of p-regions in imagers, both CCD and CMOS, and the second was a self-conducted study of white pixels caused by cosmic neutrons while the imagers are just sitting on the shelf.
Other morning sessions were on transport modeling, FUSI gates, advanced SRAM and novel integration, interface reliability, SOI and multi-gate devices, resistive switching memories, and more compound semiconductors.
In the afternoon we had advanced FEOL, non-volatile memories, advanced gate stacks, TFTs and system-on-panel, active and passive components, doping and stress simulation, silicon LEDS, and system level device modeling.
In the FEOL session UMC and Xilinx had another stress paper in which they claim simultaneous NMOS and PMOS performance improvement from a single tensile nitride layer (34.4). The key seems to be removing the nitride sidewall spacer and leaving the sidewall oxide, which results in lateral tensile stress in the channel, which enhances electron mobility, but also vertical compressive stress which improves hole mobility. They also showed that the effect is additive with memorized stress for NMOS, and wafer rotation for PMOS.
On the high-k front, Sony had some encouraging results with a damascene hafnium silicide on hafnium oxide gate stack (36.3). In the final NVM session, Samsung showed a 2 Mb FRAM smart card chip (35.6), and detailed some of the process tuning needed to pass reliability test. Freescale also demonstrated a MgO-based MRAM (35.7) tested in a 90-nm CMOS process which seemed to have potential, although it will not likely hit production for a year or two.
Summary
So that's it for the 2005 IEDM. Unfortunately many sessions were not attended, but that's the nature of this particular beast. There was significant presence from Japanese, Korean, and Taiwanese companies, with about 40% of the papers, 40% from the US, and the remaining 20% from Europe. I don't have statistics on attendees, but my guesstimate is that there was ~30% European attendees, with good representation from Philips, IMEC, ST, AMD Dresden, and Infineon. The US and Asia made up the rest with the usual large contingents from the industry stalwarts such as Intel, Samsung, IBM, etc.
All in all, it was a busy, upbeat conference, with some impressive technology to anticipate in future products. There is much more to cover in the conference digest, but it will take months to plough through its almost 1100 pages.
I'm looking forward to the first 65-nm products next year, and there were some good clues as to what we'll see at the 45-nm node. We probably won't see high-k at that node, although one or two vendors may give it a try.
DRAMs and flash memories will continue down their increasingly divergent process paths, CMOS imagers will continue to shrink (although CCDs will hang in there), and we are likely to see more creative ways of co-packaging chips to save the cost of integrating more functions on one piece of silicon.
What will we see next year? Undoubtedly more flesh on the 45-nm bones, and looking out to the 32-nm node – even though industry mavens have been forecasting the demise of silicon for years, things are not slowing down!
