Accuracy mass imaging response to IC packaging advance

Semiconductor vendors are excited by advanced packages such as flip chip, several variants of chip scale package (CSP), and System in Package (SiP). Packaging overheads are low, leading to highly miniaturized components, and electrical performance is also enhanced. These are ideal attributes for broadband applications such as IP-based voice and data communications, Gigabit and 10G Ethernet, and 3G mobile. SiP, on the other hand, offers a potentially more flexible; lower cost alternative to the System on Chip, more tolerant of redesign and inherently able to support mixed technologies.

But component assemblers need improved package assembly processes and techniques to create large area arrays, which can feature several hundred interconnects. As ever, the objectives are greater throughput, higher end of line yield, and lower capital expenditure and cost of ownership, to minimize the cost per package.

DEK has addressed these challenges with a wafer bumping solution capable of creating interconnects on a pitch as fine as 200 m, leveraging its expertise in high accuracy mass imaging. The technique is hosted by platforms that are much faster and less expensive to buy and run than traditional vapor phase deposition equipment. The tooling is at least an order of magnitude less expensive, and can be delivered within just 48 hours turnaround. In addition, the process is more tolerant of ambient conditions, occupies less factory real estate, consumes less energy, and generates less waste. Game over.

Crunch time
But high accuracy mass imaging must now prove that it can keep pace with future packaging advances. While forthcoming generations of chip scale packages aim at bump pitches significantly below 200 m and even below 150 m, the established stencil design rules are already stretched. In addition, several territories are about to launch initiatives to eliminate lead (Pb) from electronic products – either compulsorily or voluntarily. Some process issues have already come to light when screen printing with Pb-free pastes at normal SMT resolutions, but so far little is known about how these issues will manifest themselves, or be overcome, at the wafer level.

In its favor, the technique already has important users, as well as a couple of tricks up its sleeve.


Process Overview: High-Speed at Wafer-Level

High accuracy mass imaging for wafer-level applications exploits recent advances in screen printing for SMT pre-placement to create large numbers of area array interconnects at high speed. There are three key enablers: enclosed printhead technology has achieved paste volume repeatability well beyond the requirements of ordinary SMT, into wafer-level territory; precision manufacturing of electro-formed stencils, with high dimensional stability and excellent paste release characteristics; and motion controls based on linear motor technology, with new position encoders that enable high repeatability at wafer-level resolution.

The first equipment vendor to penetrate this application space, DEK, has brought other factors from the SMT equipment market to solve the challenges of commercial wafer bumping. Its flux deposition solution, for example, is faster, more repeatable and more accurate than the established offerings. There is also greater flexibility for rapid changeovers. First generation high accuracy mass imaging processes have also delivered much greater flexibility, for instance being able to deposit both solder flux and paste, or solder balls, with handling interfaces for several input formats including wafers [figure 1], singulated substrates, or substrates in carriers such as Auer boats.

In addition to these automated handling systems, further new enabling technologies have emerged to meet the needs of the semiconductor production environment, including paperless cleaning systems suitable for clean room conditions and new evolutions of the fully enclosed print head. The low waste these systems achieve is particularly important when using specialized, expensive low-alpha solder pastes for ultra-fine pitch bumping.

Wafer bumping by high accuracy mass imaging does require the utilization of unique design guidelines tailored for each application, and much work has already been done to establish suitable guidelines for bump pitches and solder paste characteristics in common use. In addition, specific equipment, materials and process instructions need to be followed to establish a robust, high-yield wafer bumping print and reflow procedure.

In the imaging step, an over-printing strategy is used to achieve bump height targets of 80 to 150 microns on pitches of 150 up to 500 microns [figure 2]. This technique requires rigorous application of design rules when creating the stencil. It is also necessary to pay careful attention to the design of bond pads, allowing sufficient contact area to achieve sufficient solder joint strength for a given stand-off.

The size of the pads on the chip has a direct influence on solder volume requirements. Smaller pads require less paste than larger pads to achieve the same target reflowed bump height. When the pad size is too small, however, less bonding area is available to support a relatively large volume of solder. Thus, bump and solder joint strength may be sacrificed for only slight gains in standoff distance.

Solder bump sizes also are affected by the shape of the wettable bonding area of the chip pads. This shape is not necessarily dependent on the geometry of the pads, but is chiefly determined by the passivation opening overlying the pads.

In a typical example, solder paste is deposited through apertures measuring 6 x 19 mils and 3 mils deep. On reflow, the paste retracts onto the pad, forming spheres 5 mils high and 6 mils in diameter [figure 3]. Generally, this process is suitable for bumping pitches down to 200 micron for full array die and 150 micron for peripheral array designs.

Emerging Challenges, New Tricks
As bump pitches shrink, the volume of each solder bump will also reduce. Paste volume repeatability therefore becomes even more important, if coplanarity is to be maintained. There are two aspects to achieving high paste volume repeatability: 100 percent aperture filling, which the enclosed printhead delivers; and optimal paste release. A new technique is emerging to enhance paste release for wafer-level applications.

When screen printing with a traditional emulsion screen and squeegee, the stencil tends to peel away from the substrate surface, resulting in a progressive reduction of adhesion between the paste and the stencil until the stencil separates fully from the substrate. This has a beneficial effect on both paste transfer efficiency and repeatability. But the majority of today's mass imaging processes – including semiconductor assembly processes - feature a metal stencil, such as a laser cut stencil. This is brought into direct contact with the substrate before the squeegee or enclosed head begins its excursion. Afterwards, the substrate is moved directly downwards away from the stencil. The combination of forces that result in the peeling action are thus replaced by a vertical pulling force.

By investigating the movement of metal stencils during separation, DEK noted that separation actually begins at each outside edge of the stencil and converges towards its center. The center is the last part of the stencil to release. This separation also accelerates towards the center of the stencil, which does not make for consistent paste release.

Regaining the peeling action displayed when a conventional emulsion screen separates [figure 4] is crucial to developing a repeatable process for bump pitches of 150 m and below. To achieve this, DEK has developed an optimized stencil tensioning mechanism, combined with a radically different separation action. The frame is capable of automatically adjusting the tension within the foil to optimize both the deposition and separation phases of the process. The tension is adjusted pneumatically, using the standard air supply available on any automated mass imaging platform.

Responding to Pb-free
Wafer bumping must also respond to the industry-wide migration to lead (Pb)-free solder alloys. Pastes manufactured with these alloys are now known to display a different rheology from their Pb-rich predecessors. SMT assemblers are now finding that they must subtly alter their screen printing parameters in order to optimize processes for Pb-free printing. The same will be true at the wafer level, where the higher viscosity and greater metal content of the new pastes will have implications for aperture filling, paste on pad, and shrinkage during reflow. Responses will likely come in the form of revised design rules for both pads and apertures. Research into Pb-free screen printing for SMT applications has shown the process is now sensitive to stencil separation speed. This adds an extra dimension when calculating the process window. Research into separation speed, as well as putting the peel back into the separation action – as discussed above – are important avenues for Pb-free wafer bumping research.

The high metal content of Pb-free pastes implies lower shrinkage during reflow. As a result, there will be a closer relationship between bump height and standoff height. Process developers need to fully understand these relationships to determine the paste volume required to achieve a target bump height, and design pads and corresponding stencil apertures accordingly. Pad design will also impact solder joint reliability, since this is a function of standoff height.

In addition, Pb-free pastes have lower wetting forces, and show less inclination to "pull" the solder onto the pad in the event of a small mis-registration: stencil-to-wafer alignment, as well as stencil quality and fidelity for high paste on pad repeatability, will be critical in Pb-free wafer level applications.

It is also worth noting that Pb-free pastes are more expensive than their Pb-rich ancestors, as a result of their higher tin content and the addition of silver and copper. Manufacturers will become more aware of the high cost of wasted paste, and will appreciate the arrival of new low volume enclosed printhead designs. In fact, these are already well established, following development of low volume ProFlow® transfer heads for printing conductive vias and for use with high-value low-alpha pastes. These print head technologies will likely transfer directly into Pb-free wafer bumping applications.

High accuracy mass imaging is bringing the speed and cost advantages of stencil printing principles to advanced packaging assembly applications. But the demands are continually changing, calling for more I/Os and progressively smaller interconnect pitch, as well as the challenges of Pb-free assembly. Further research and development, as well as adoption of new techniques already in the pipeline aimed at increasing repeatability for very low volume deposits, will enable next generation packages at commercial volumes and prices.