News Article
Silicon Design Chain collaboration extends 90-nanometer low-power design into the mainstream
Over the past two decades, the once vertically integrated electronics industry has fragmented into a multi-layered network of horizontal suppliers. This disaggregation has complicated the supply chains associated with designing and manufacturing products, and it has created an increasingly complex design chain for the development of end-product designs.
Over the past two decades, the once vertically integrated electronics industry has fragmented into a multi-layered network of horizontal suppliers. This disaggregation has complicated the supply chains associated with designing and manufacturing products, and it has created an increasingly complex design chain for the development of end-product designs.
Given the size and scope of the challenge posed by disaggregation, no one company can solve it alone. In early 2003, recognising the need to collaborate on joint solutions, industry leaders Applied Materials, ARM, Artisan Components, Cadence and TSMC formed the Silicon Design Chain Initiative. Combining their expertise, these companies have established a charter to drive programs designed to address the top issues facing our customer's in the electronics industry, including the toughest challenges in nanometer digital IC design.
Early in 2004, the Silicon Design Chain members concluded that their respective customers were encountering the same design barrier managing power consumption at advanced process nodes.
The low power gap
From portable digital music players to phones that send photos and surf the web, a new generation of mobile electronics products is pressing electronics makers to extend battery life while improving performance for the on-demand era. However, while advances in CMOS technology have allowed engineers to pack twice as many transistors onto the same area of silicon every 18 months, battery technology has failed to keep pace. An equivalent doubling of battery performance has taken more than five years on average, leaving a critical power gap.
In addition to battery life, a new generation of consumers also expects to see more cool features and performance packed into increasingly smaller devices, compelling chip developers to adopt advanced process nodes. This compounds power consumption issues, because power consumption jumps dramatically when silicon geometries shrink below 130nm due to growing leakage effects. In fact, today's nanometer-scale chips can use nearly as much power when idle as they do when operating.
In addition to mobile and handheld devices—where battery life is the key concern—problems associated with power consumption extend to wired devices as well. Power translates into heat, and chips are heating up dramatically as power density (watts per square centimeter) grows along with skyrocketing transistor counts. One example is the latest generation of high-performance microprocessors, which often have power requirements that exceed 100 watts.
In these massively integrated circuits, power dissipated as heat also becomes a major concern in the overall system design. Maintaining reliable operating temperatures for chips in this power range requires large, intricate heat sinks, expensive packages and special cooling environments. In the worst scenario, if heat could not be dissipated adequately, the device would not meet the performance requirements. With state-of-the-art chips such as graphic processors, where speed is of the essence, companies cannot sacrifice performance using traditional methods to save power and still remain competitive in the market.
As performance requirements grow and 90-nanometer (nm) processes proliferate, the demand for extending battery life increases and chips get hotter. Power management has thus become one of the most critical hurdles for designers to overcome.
Silicon Design Chain members tackle the low-power problem
Members of the Silicon Design Chain recently collaborated to develop a cross-industry solution for power management. The result is an effective integrated power management system that works across the design chain.
This system has already been validated with the successful implementation of a chip based on the ARM1136JF-S core module that will be available from ARM in reference boards. The device, aimed at mobile and wireless applications, yielded greater than 40% savings in power consumption. To ensure that this low-power solution would be usable in the real world, it employed typical methods, including the TSMC 90nm G silicon process. It also used general-purpose Artisan physical IP, including SAGE-X standard
cell libraries and memory generators that were augmented with extended voltage range characterization and cells aimed at enabling power reduction design techniques. Cadence developed a low-power design methodology using version 4.1 of the Encounter digital IC design platform.
The power reduction approach
The Silicon Design Chain team set out to prove that their low-power design system could dramatically reduce both dynamic and leakage power consumption on their ARM1136 design.
Dynamic power reduction
The first focus of the design team was to attack dynamic power. Dynamic power consumption can be represented by the formula:
P = KC V2F
K: toggle rate—fraction of time transistors are switching
C: circuit capacitance
V: supply voltage to transistors
F: operating frequency
Voltage scaling
Because the power is proportional to the square of the supply voltage, a significant amount of dynamic power can be saved by simply reducing the voltage. However, the project had very strict performance targets. The design needed to be able to perform to 350MHz to meet the development requirements of ARM's partners. Since lowering the supply voltage slows down the speed at which transistors can switch, the team had to be selective in determining which parts of the design could have their voltage reduced
(this technique is known as “voltage scaling”). They partitioned the design into “voltage domains” (also called “voltage islands”).
In this type of multi-supply voltage (MSV) design, each domain operates at a different supply voltage depending on its timing characteristics. The team chose to keep the blocks that are timing critical in one domain operating at the standard 90nm supply voltage of 1.0V. The less timing critical blocks were aggregated into a second domain, with the voltage scaled down to 0.8V, thereby saving 36% of the dynamic power for that portion of the design.
A challenge with voltage scaling is the need to translate the voltages for the signals that interface between voltage domains. This is accomplished by inserting “level shifters,” which are special cells that perform voltage translation, and clamp cells to provide isolation. Artisan level shifters include integrated clamps.
The ARM1136 core design had 3400 signals that went from the 0.8V to the 1.0V domains. This meant that the team needed to insert 3400 level shifters. Traditionally, this would have been a manual process requiring significant error-prone human effort. The low-power design system has automated the process of inserting level shifters into the design, hooking them up to the two power rails and optimising their placement for area and timing.
Additionally, Cadence and Artisan collaborated to create level shifters optimized for use with the Cadence Encounter NanoRoute routing engine. The level shifter design and the automation of their implementation into the ARM1136 core design is a key enabler to getting significant dynamic power reduction and still meeting aggressive schedule requirements.
Clock gating
Additional dynamic power reduction was achieved via clock gating. In many instances, data is loaded into registers only infrequently, but the clock signal continues to switch at every clock cycle, which drives a capacitive load. To prevent the clock network from switching, a gating circuit can be used to shut off the clock for these registers. Clock gating alone can result in a 10 to 20% dynamic power savings.
The Silicon Design Chain low-power project used Cadence Encounter RTL Compiler to perform automated clock gating, using integrated clock-gating cells from the Artisan library. Encounter RTL Compiler recognises clock-gating opportunities in the RTL or gate-level netlist, and inserts clock-gating cells automatically. This automated capability enabled the design team to gate 85% of the registers in the lowpower chip. This combination of new methodologies—voltage scaling and clock gating—allowed the Silicon Design Chain team to tape-out a chip with a 38% decrease in dynamic power consumption.
Static power reduction
The next challenge the design team addressed was leakage power. As transistor lengths have gotten smaller, leakage currents have become a significant source of power consumption. Because the ARM1136 core design was being manufactured in a 90nm process, leakage current could account for as much as 50% of the overall power consumed.
The approach the team took to manage leakage power dissipation was to use libraries from Artisan that contained a matched set of logic cells, each having different threshold voltages (Vt) and the same physical footprint. The cells with the higher threshold voltage leak less than their counterpart cells with lower Vt. However, these High-Vt cells run slower than their lower Vt counterparts. To meet the 350MHz performance goal while minimizing the overall leakage current, the team first optimised the design during synthesis using Encounter RTL Compiler. The big advantage of using this technology over traditional synthesis tools is that it is able to optimise for power, performance and area concurrently. This enabled the team to come up with a netlist implementation that met performance at the lowest possible leakage current. After place-and-route, the design was then tuned to provide the final optimisation that accounted for the actual wires.
Using this improved static power reduction methodology allowed the Silicon Design Chain design team to achieve 46.7% savings in leakage power.
Timing analysis and ECSM
Once power was optimised, the team needed to perform analysis and verification of the low-power design. Using multiple power supplies within the chip complicates the timing analysis step because the tools need to have accurate delay models for each operating voltage when computing the timing. Proper modeling for level-shifter and clamp cells is also needed to compute the delays correctly. The effective current source model (ECSM) helps solve these issues at 90nm.
Unlike traditional modeling, which models voltage, ECSM, models the current drawn by transistors. The ECS-based standard cell models used in the Silicon Design Chain chip achieved delay prediction that correlated, on average, to within 0.5% of SPICE.
For the project, Artisan characterised their 90-nm libraries to support ECSM delay prediction, by providing lib_ecsm library views. In multi-supply voltage (MSV) designs, different operating voltages can be covered with ECSM models, characterised at just three points across the voltage range.
For additional details, please visit:
http://www.cadence.com/datasheets/ArtisanMSMV_tp.pdf
Design sign-off
Accuracy was a primary concern when signing off the low-power chip. The Silicon Design Chain utilized VoltageStorm and CeltIC NDC to provide the required accuracy. VoltageStorm was used to analyse the IR drop across the 1.0V and 0.8V power grids showing that each transistor in the design is operating with a unique supply voltage. The resultant voltages were input into the ECSM-based delay calculator in CeltIC NDC (SignalStorm). This provided near-SPICE accurate timing across the two supply voltage regions. This is critical because the IR drop effect on timing is accentuated at lower supply voltages utilised in MSV design.
Conclusion
The emerging market opportunities in electronics can only be realised by rapidly and cost effectively addressing nanometer-scale design chain challenges. The Silicon Design Chain member companies are collaborating to tackle those tough cross-industry issues. The team has validated in silicon ARM's industry-standard ARM1136JF-S wireless processor in TSMC's 90G process using a low-power design system
comprised of ARM's finely tuned physical IP products and modeling methodology combined with Cadence's Encounter low-power design flow. Together, the solution will reduce the risks associated with moving to advanced process nodes for mainstream electronics product developers.
Given the size and scope of the challenge posed by disaggregation, no one company can solve it alone. In early 2003, recognising the need to collaborate on joint solutions, industry leaders Applied Materials, ARM, Artisan Components, Cadence and TSMC formed the Silicon Design Chain Initiative. Combining their expertise, these companies have established a charter to drive programs designed to address the top issues facing our customer's in the electronics industry, including the toughest challenges in nanometer digital IC design.
Early in 2004, the Silicon Design Chain members concluded that their respective customers were encountering the same design barrier managing power consumption at advanced process nodes.
The low power gap
From portable digital music players to phones that send photos and surf the web, a new generation of mobile electronics products is pressing electronics makers to extend battery life while improving performance for the on-demand era. However, while advances in CMOS technology have allowed engineers to pack twice as many transistors onto the same area of silicon every 18 months, battery technology has failed to keep pace. An equivalent doubling of battery performance has taken more than five years on average, leaving a critical power gap.
In addition to battery life, a new generation of consumers also expects to see more cool features and performance packed into increasingly smaller devices, compelling chip developers to adopt advanced process nodes. This compounds power consumption issues, because power consumption jumps dramatically when silicon geometries shrink below 130nm due to growing leakage effects. In fact, today's nanometer-scale chips can use nearly as much power when idle as they do when operating.
In addition to mobile and handheld devices—where battery life is the key concern—problems associated with power consumption extend to wired devices as well. Power translates into heat, and chips are heating up dramatically as power density (watts per square centimeter) grows along with skyrocketing transistor counts. One example is the latest generation of high-performance microprocessors, which often have power requirements that exceed 100 watts.
In these massively integrated circuits, power dissipated as heat also becomes a major concern in the overall system design. Maintaining reliable operating temperatures for chips in this power range requires large, intricate heat sinks, expensive packages and special cooling environments. In the worst scenario, if heat could not be dissipated adequately, the device would not meet the performance requirements. With state-of-the-art chips such as graphic processors, where speed is of the essence, companies cannot sacrifice performance using traditional methods to save power and still remain competitive in the market.
As performance requirements grow and 90-nanometer (nm) processes proliferate, the demand for extending battery life increases and chips get hotter. Power management has thus become one of the most critical hurdles for designers to overcome.
Silicon Design Chain members tackle the low-power problem
Members of the Silicon Design Chain recently collaborated to develop a cross-industry solution for power management. The result is an effective integrated power management system that works across the design chain.
This system has already been validated with the successful implementation of a chip based on the ARM1136JF-S core module that will be available from ARM in reference boards. The device, aimed at mobile and wireless applications, yielded greater than 40% savings in power consumption. To ensure that this low-power solution would be usable in the real world, it employed typical methods, including the TSMC 90nm G silicon process. It also used general-purpose Artisan physical IP, including SAGE-X standard
cell libraries and memory generators that were augmented with extended voltage range characterization and cells aimed at enabling power reduction design techniques. Cadence developed a low-power design methodology using version 4.1 of the Encounter digital IC design platform.
The power reduction approach
The Silicon Design Chain team set out to prove that their low-power design system could dramatically reduce both dynamic and leakage power consumption on their ARM1136 design.
Dynamic power reduction
The first focus of the design team was to attack dynamic power. Dynamic power consumption can be represented by the formula:
P = KC V2F
K: toggle rate—fraction of time transistors are switching
C: circuit capacitance
V: supply voltage to transistors
F: operating frequency
Voltage scaling
Because the power is proportional to the square of the supply voltage, a significant amount of dynamic power can be saved by simply reducing the voltage. However, the project had very strict performance targets. The design needed to be able to perform to 350MHz to meet the development requirements of ARM's partners. Since lowering the supply voltage slows down the speed at which transistors can switch, the team had to be selective in determining which parts of the design could have their voltage reduced
(this technique is known as “voltage scaling”). They partitioned the design into “voltage domains” (also called “voltage islands”).
In this type of multi-supply voltage (MSV) design, each domain operates at a different supply voltage depending on its timing characteristics. The team chose to keep the blocks that are timing critical in one domain operating at the standard 90nm supply voltage of 1.0V. The less timing critical blocks were aggregated into a second domain, with the voltage scaled down to 0.8V, thereby saving 36% of the dynamic power for that portion of the design.
A challenge with voltage scaling is the need to translate the voltages for the signals that interface between voltage domains. This is accomplished by inserting “level shifters,” which are special cells that perform voltage translation, and clamp cells to provide isolation. Artisan level shifters include integrated clamps.
The ARM1136 core design had 3400 signals that went from the 0.8V to the 1.0V domains. This meant that the team needed to insert 3400 level shifters. Traditionally, this would have been a manual process requiring significant error-prone human effort. The low-power design system has automated the process of inserting level shifters into the design, hooking them up to the two power rails and optimising their placement for area and timing.
Additionally, Cadence and Artisan collaborated to create level shifters optimized for use with the Cadence Encounter NanoRoute routing engine. The level shifter design and the automation of their implementation into the ARM1136 core design is a key enabler to getting significant dynamic power reduction and still meeting aggressive schedule requirements.
Clock gating
Additional dynamic power reduction was achieved via clock gating. In many instances, data is loaded into registers only infrequently, but the clock signal continues to switch at every clock cycle, which drives a capacitive load. To prevent the clock network from switching, a gating circuit can be used to shut off the clock for these registers. Clock gating alone can result in a 10 to 20% dynamic power savings.
The Silicon Design Chain low-power project used Cadence Encounter RTL Compiler to perform automated clock gating, using integrated clock-gating cells from the Artisan library. Encounter RTL Compiler recognises clock-gating opportunities in the RTL or gate-level netlist, and inserts clock-gating cells automatically. This automated capability enabled the design team to gate 85% of the registers in the lowpower chip. This combination of new methodologies—voltage scaling and clock gating—allowed the Silicon Design Chain team to tape-out a chip with a 38% decrease in dynamic power consumption.
Static power reduction
The next challenge the design team addressed was leakage power. As transistor lengths have gotten smaller, leakage currents have become a significant source of power consumption. Because the ARM1136 core design was being manufactured in a 90nm process, leakage current could account for as much as 50% of the overall power consumed.
The approach the team took to manage leakage power dissipation was to use libraries from Artisan that contained a matched set of logic cells, each having different threshold voltages (Vt) and the same physical footprint. The cells with the higher threshold voltage leak less than their counterpart cells with lower Vt. However, these High-Vt cells run slower than their lower Vt counterparts. To meet the 350MHz performance goal while minimizing the overall leakage current, the team first optimised the design during synthesis using Encounter RTL Compiler. The big advantage of using this technology over traditional synthesis tools is that it is able to optimise for power, performance and area concurrently. This enabled the team to come up with a netlist implementation that met performance at the lowest possible leakage current. After place-and-route, the design was then tuned to provide the final optimisation that accounted for the actual wires.
Using this improved static power reduction methodology allowed the Silicon Design Chain design team to achieve 46.7% savings in leakage power.
Timing analysis and ECSM
Once power was optimised, the team needed to perform analysis and verification of the low-power design. Using multiple power supplies within the chip complicates the timing analysis step because the tools need to have accurate delay models for each operating voltage when computing the timing. Proper modeling for level-shifter and clamp cells is also needed to compute the delays correctly. The effective current source model (ECSM) helps solve these issues at 90nm.
Unlike traditional modeling, which models voltage, ECSM, models the current drawn by transistors. The ECS-based standard cell models used in the Silicon Design Chain chip achieved delay prediction that correlated, on average, to within 0.5% of SPICE.
For the project, Artisan characterised their 90-nm libraries to support ECSM delay prediction, by providing lib_ecsm library views. In multi-supply voltage (MSV) designs, different operating voltages can be covered with ECSM models, characterised at just three points across the voltage range.
For additional details, please visit:
http://www.cadence.com/datasheets/ArtisanMSMV_tp.pdf
Design sign-off
Accuracy was a primary concern when signing off the low-power chip. The Silicon Design Chain utilized VoltageStorm and CeltIC NDC to provide the required accuracy. VoltageStorm was used to analyse the IR drop across the 1.0V and 0.8V power grids showing that each transistor in the design is operating with a unique supply voltage. The resultant voltages were input into the ECSM-based delay calculator in CeltIC NDC (SignalStorm). This provided near-SPICE accurate timing across the two supply voltage regions. This is critical because the IR drop effect on timing is accentuated at lower supply voltages utilised in MSV design.
Conclusion
The emerging market opportunities in electronics can only be realised by rapidly and cost effectively addressing nanometer-scale design chain challenges. The Silicon Design Chain member companies are collaborating to tackle those tough cross-industry issues. The team has validated in silicon ARM's industry-standard ARM1136JF-S wireless processor in TSMC's 90G process using a low-power design system
comprised of ARM's finely tuned physical IP products and modeling methodology combined with Cadence's Encounter low-power design flow. Together, the solution will reduce the risks associated with moving to advanced process nodes for mainstream electronics product developers.
