Solving the MCP Memory Challenge

Multi-chip packages (MCPs), in which various types of memory required for these devices are included in a single package, have become the standard for mobile phones with nearly all modern mobile phones including at least one MCP. Using MCPs allows manufacturers to offer the new multi-function devices while maintaining small form factors. MCPs offer a small footprint at low cost with reasonable flexibility.

Because the MCP only includes memories, the design of the processor is independent of the memory specifics, which is important given the fast turns and short life cycles of DRAM and NAND. While SiP and PoP, and other technologies such as PiP (Package-in-Package), are being adopted for the 3D packaging market, MCPs are expected to continue to dominate for the next five years.

The biggest challenge to MCP use has been finding an economic testing solution. As a leader in semiconductor test, Agilent has been at the forefront of developing solutions to this challenge to enable the market's continued adoption of MCPs.

Why Standard Testers Don't Work Well for MCPs
The first MCPs going into mobile phones were relatively simple to test. Comprising of a NOR Flash and an SRAM with similar address protocols the two memories shared their address and data busses, and where thus the MCP had a similar pin count to a standard NOR Flash. As phones have been required to do more than just transmit voice, phone manufacturers have responded by adding an applications processor, which means that the SDRAM resides on a higher performance bus. In addition, the NAND Flash, which provides nonvolatile high density data storage, may reside on yet another bus because of its lower performance and significantly different protocol. Now a typical stack of these memories might reside on three busses: a NOR/SRAM bus, a higher performance SDRAM bus and a NAND bus. No longer a simple memory device, today's MCPs may have as many as 133 signal pins, including 66 bi-directional pins.

The current standard method for testing complex MCPs like the one described above, is to test them on multiple testers. First, the SDRAM is tested on a DRAM tester. The MCP is then transferred to another tester with another loadboard that connects the NOR/SRAM to be tested. Finally, the MCP is moved to a third tester, where yet a third loadboard connects the NAND to be tested. The three insertions increase the total test time of the MCP, the number of load boards needed for each device, and overall test floor complexity, raising the overall cost of test and tripling the yield-loss due to parts that are damaged through handling.

While a standard memory tester reduces the cost of test by testing as many devices in parallel as possible, perhaps up to 256 on one head, they are limited to testing devices with less than 64 pins, which is not sufficient for the complex MCP described above. This problem is further exacerbated with DRAM testers, which have a limited number of bi-directional pins, often as few a 9 per site.

Using a tester that supports testing of devices with more than 64 pins would solve the multiple insertion problem, but because the SRAM and DRAM finish testing much more quickly than the NOR and NAND, it would result in a low utilization of tester resources. If the memories must be tested sequentially, then the tester resources connected to the memories not currently under test sit idle: this could be as much as twothirds of the tester being idle on average. In both of these scenarios, one is paying for resources which may sit idle most of the time.

Design Challenge: Enabling Maximum Utilization and Managing Costs
The solution to this MCP testing challenge as it was conceived by the test system designers at Agilent Semiconductor Test Solutions was to develop a software re-routable interface technique for connecting tester resources to the specific pins being tested at a specific point in the flow to allow for testing the MCP in a single insertion and at a high parallelism, while ensuring the highest tester utilization. Yet, as with many ideas, complications lie in the details.

The first obstacle lies in the sheer number of signals to be rerouted. If forty signals per device must be reroutable to one of four device pins, a minimum of 120 relays per site are required. If sixtyfour devices are tested in parallel, 7680 relays are required. Not only does this take up a tremendous amount of space and burn a great deal of power, but it creates a significant reliability risk.

Discrete FET switches help with the board space, but have their own issues. Their capacitance and trace length stubs can impact the frequency performance to the device under test. If MCPs only had Flash, the performance degradation might be acceptable, but mobile SDRAMs are already running at 133MHz, and mobile games will surely drive even higher performance. High performance FETs are available, but these are quite sensitive to ESD (electro-static discharge), and thus a liability from the reliability perspective.

Ultimately it was determined that the use of a highperformance ASIC would resolve many of these issues. Trace length stubs are minimized, and tremendous switching densities can be achieved. However, the long lead times and high development cost for such an ASIC required that this switching matrix be deviceindependent. It would be costprohibitive to redesign this matrix for every device that is to be tested. An additional interface layer is needed which creates additional challenges because it requires a high density, highly reliable, and high performing interconnect be used. Additionally, every tester channel must have the same functionality. Otherwise, the routing from the switching matrix to the device pin will be extended, degrading performance and adding channel capacitance.

The flexibility of having all identical channels also offers the benefit of reusing the device-specific interface or socket board. Because MCPs are designed for a specific mobile appliance, there is no consistency in pinouts for a given package. While JEDEC is attempting to mitigate this by setting standards, ever increasing time-to-market pressure drives vendors to reuse package designs for various stacks. Thus, pin M5 may be an I/O for a NAND Flash for one MCP, and it may be an address pin for a NOR Flash on another MCP. The tester must therefore be able to deliver a clock, address, or I/O signal to any pin. If the tester manufacturer has reduced cost by optimizing channels to deliver specific functionality to a channel, the correct type of tester channel will have to be routed to the pin for that specific device. Each MCP will thus require its own specific interface board. This cost is further exacerbated as device life cycles continue to decrease.

The Kiowa: Performance Comes in a Small Package
The central component of Agilent's Programmable Interface Matrix is the Kiowa high performance ASIC. Each one of these ASICs has the capability of switching eight tester channels between sixtyfour device pins. To accommodate 1024 of these per test head, a 100 pin CSP (Chip Scale Package) was chosen. The high speed serial bus minimizes the number of traces that must be run to each ASIC, resulting in a less complex, smaller board.

In order to achieve the required performance, the switching matrix cannot increase the signal path capacitance substantially; increased capacitance will slow down the rise times of high performance memories, and many lower performance mobile memories cannot drive a highly capacitive line. To this end, line capacitance was minimized by simplifying the signal path as much as possible and using lowcapacitive gates. The routing was implemented so as to minimize the stub length for each switch path, as each stub increases the capacitance for the line. Finally, each channel is isolated from the other three channels in order to minimize any crosstalk between channels.

Due to the static that can build up as parts are inserted into a socket, ESD (Electro-Static Discharge) had to be taken into account. In addition to diode-clamping the ground and supply pins, each tester channel is connected to a low ESR (Equivalent Series Resistance), low inductance 100nF capacitor. The slight decrease in performance from the increased line capacitance is well justified by the increased reliability of the switch. By providing the switching equivalent of 64 relays in a small, reliable package, the high performance Matrix ASIC is a key technology that enables the massive signal switching necessary for economical (high-parallelism) testing of Multi-Chip Package memories.

Reducing the cost of testing MCPs
The use of a switching network in conjunction with an all I/O tester increases tester resource utilization when testing MCPs, which allows for higher parallelism and shorter test times. The switching network also allows complex MCPs to be tested in one insertion, eliminating the need for multiple load board designs for each new MCP. These increasing densities will continue to drive the higher level of integration that multi-chip packages provide. As the stacks grow higher, providing economic testing becomes increasingly difficult. As shown in table 1, a switching matrix can reduce the cost of test of these devices by up to 75%.