Mentor Graphics and ARM validate physical IP
The Mentor team had access to the latest ARM Metro standard cells for a 65nm Low Power "LP" process variant, and worked closely with ARM to verify the results of the evaluation. The analysis shows that ARM physical IP exhibits excellent placement context independence in cell printability and performance. Placement context independence allows cells to be placed next to any other cell without degradation in yield or electrical performance, which should lead to predictable performance and robust manufacturability across designs and process windows at 65nm.
"The implications of this study are very important as they demonstrate that our design methodology for 65nm creates highly manufacturable physical IP," said Neal Carney, vice president of Marketing, Physical IP, ARM. "The fact that ARM physical IP proved to be robust, via independent validation of our current flow, is a proof point in ARM providing high-quality IP solutions to meet our customers' SoC design requirements."
"ARM has proven that their physical IP is robust across a 65nm process window using Calibre LFD," said Joe Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "The results of the research establish the importance of evaluating physical IP based on context dependency and layout robustness to lithographic variations across process window."
