Matsushita selects Mentor Graphics for manufacturing nanometer technology
Process variability can have a dramatic effect on yield. This is especially true in the lithographic process where variability puts image fidelity at risk even when the operating conditions of the lithographic system (lithographic process window) are acceptable. To reduce the risk of silicon failure, avoid costly respins of both masks and silicon and safeguard time-to-market schedules, Calibre OPCverify detects lithographic errors or marginalities caused by process variability before the design goes to the mask or wafer manufacturer.
"Verification of post-OPC output is critical to minimizing mask respins of million dollar mask sets, and avoiding time-to-market delays," said Hiroyuki Tsujikawa, Semiconductor Company, Matsushita Electric Industrial Co., Ltd. "Building on the Calibre platform for nanometer technologies has enabled Matsushita to develop a world-class process and gain a competitive advantage in delivering a wide range of System LSI."
"For 90nm and smaller technology nodes, the complexity of OPC and the constraints that go with it require verification to prevent silicon failures," said Joe Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "Mentor is pleased to have Matsushita join the large and growing ranks of top semiconductor companies who have adopted our production proven verification platform."
