Ponte Solutions collaborates with UMC
Ponte's methodology helps reducing manufacturing cost and time-to-volume production of complex semiconductor ICs by revealing yield-sensitive areas of libraries, IPs, memories and full chip designs and enabling yield improvement at the design stage, prior to committing to expensive fabrication.
"IC designers have realized the benefits of proactive yield sensitivity analysis in deep sub-micron technologies," said Ken Liou, director of the IP and Design Support Division at UMC.
"Ponte's Yield Analyzer provides Defect Limited Yield information which can be used by tools at virtually every step of the design flow starting from library/IP design and characterization to netlist generation, floorplanning, full chip detailed routing and ECO. Using Yield Analyzer, designers can use DD (Defect Density) data to analyze two or more layouts to evaluate and decide the best option for tape-out based on their requirements."
"We strongly believe that yield, traditionally the domain of fabs, must become a driving factor behind sub-90nm design flows," said Alex Alexanian, CEO of Ponte Solutions. "Ponte anticipated this trend more than two years ago and has worked with technology partners to develop and validate the accuracy, performance and usability of Yield Analyzer as design-stage yield characterization and analysis tool. Our partnership with UMC is an important milestone in bringing yield driven design methodologies to the design community."