Device Construction

Thin WSix insertion in tungsten gate stacks

Gate oxide integrity is an increasing concern for leading edge devices. For DRAM one seeks both reliability and high speed performance. Inserting a thin WSix (Tungsten Silicon) layer in tungsten poly gate stack to relieve the mechanical stress of gate hard mask nitride films could lead to better gate oxide reliability and stress immunity of DRAM transistors. This insertion also could prevent the formation of a SiN dielectric layer on top of the poly-Si, lowering the contact resistance between the poly and the tungsten layers. Here, Hynix researchers report on reduced contact resistance and significant improvements in gate oxide reliability from WSix/WN double diffusion barriers.

As a candidate for the gate electrode stack for high speed memory devices (DRAM), the tungsten poly-metal (W/WN/poly-Si) gate electrode has much lower resistance than conventional tungsten polycide (WSix/poly-Si) gate stacks [1]. The W/WN/poly-Si stack can also reduce capacitance-equivalent-thickness (CET) compared with WSix/poly-Si, due to the fluorine-free nature of the W deposition process.

However, there exist some disadvantages for the W/WN/poly-Si gate, such as abnormally high stress-induced leakage currents (SILC) and interface trap densities (Dit) (trap states near the midgap). These effects are not seen in the WSix/poly-Si stack (Figure 1). SILC and Dit are known to be caused mainly by the stress mismatching between the nitride hard mask layer and the W/WN/poly-Si stack [2]. This hard mask nitride has been widely used for self-aligned contact (SAC) processes in DRAM technology to ensure a reliable landing-pad formation. To reduce hard mask nitride induced mechanical stress, we inserted diffusion barriers such as WSix or Ti/TiN between the WN and poly-Si with a thick hard mask nitride film on the gate stack, and investigated their gate oxide reliability characteristics.

Recently, WSix/WN or Ti/TiN/WN diffusion barriers have shown W-poly interfacial contact resistances (Rc) lower than for conventional W/WN/poly-Si gate stack [3, 4], but there is no report on the mechanism for reduced gate Rc. Such knowledge could guide the choice of new diffusion barrier metals in W poly gates. One seeks both better gate oxide integrity (GOI) and low gate Rc for future DRAM gate stacks leading to improved reliability and high speed performance. Tungsten poly gated metal oxide semiconductor (MOS) capacitors and MOS field effect transistors (MOSFET) with shallow-trench isolation (STI) were fabricated on 200mm diameter p-type (100) Si substrates. In situ phosphorus-doped poly-Si (70nm) was deposited after gate oxidation (~5.5nm). We prepared three samples with different gate electrode structures as summarized in Figure 2.

The first was a conventional W (30nm)/WN (5nm) stack deposited on the poly-Si for comparison purposes. The second and third involved inserting two thin layers of Ti (3nm) and TiN (4nm) or a single WSix (10nm) layer between the WN and poly-Si layer as additional diffusion barriers. The Ti and TiN layers were deposited by reactive sputtering and the WSix layer was deposited by chemical vapour deposition (CVD). The WN/W electrodes were reactive sputterdeposited, followed by nitride deposition (250nm) by plasmaenhanced chemical vapor deposition (PECVD). MOS capacitors or MOSFETs were then fabricated by photolithography and reactive ion etching.

Stress relief
The temperature-dependent film stress behaviour of the various gate electrode stacks was analyzed via thermal cycling from room temperature to 900°C. Figure 3 shows measured mechanical film stress hysteresis curves on the various gate stacks during heating and cooling cycles. The arrows in Figure 3a denote the direction of the heating (bottom) and cooling (top) cycles for the various gate stacks. The hysteresis curve is considered to be created by the densification of PECVD hard mask nitride which contains hydrogen and thermally unstable Si-H and N-H bonding during thermal processing [5]. To quantify the amount of thermal stress, each hysteresis curve was integrated. The results are shown in Figure 3b. We observe a noticeable decrease in hysteresis area for the WSix inserted gate stack. However, the Ti/TiN inserted gate stack results in a slight increase in area.

To investigate the effect of stress relief with WSix insertion in the W poly gate stack, we additionally measured thermal stress values of W/WN/WSix/poly gate stacks which have different thickness values of inserted WSix, and also for W/WN/poly and WSix/poly gate stacks (Figure 4). We can clearly see that the hysteresis area decreases as the thickness of inserted WSix layer increases. Comparatively, the W/WN/poly gate stack shows the largest hysteresis area and the WSix/poly gate stack exhibits the lowest value, respectively.

Since amorphous WSix film (as-grown) transforms into a poly-crystalline structure after post thermal anneal up to 900°C, the structural change of the inserted WSix layer may be the main reason why the inserted WSix layer absorbs the mechanical stress caused by the gate hard mask nitride during thermal processing.

The cross sections of the interface between the gate oxide and poly-Si were microscopically examined by TEM (Figure 5). The examined samples have different thicknesses of inserted WSix layer between the poly-Si and WN. A large poly void was observed in the gate oxide for the stack without inserted WSix (Figure 5a). The creation of the poly void is considered to be precipitated by the locally enhanced diffusion of silicon through the poly-Si grain boundary due to the non uniform mechanical stress of the hard mask nitride during post thermal processing [6].

We see that the size of poly void decreases as the thickness of inserted WSix increases (Figures 5b and c). No void was measured for the WSix inserted stack with a thickness of 70nm (Figure 5d).

The insertion of WSix into the W poly stack absorbing the stress from the hard mask nitride is believed to prevent excessive out diffusion of silicon from the poly-Si. Therefore, the reduced size of poly voids with WSix insertion in the gate stack could contribute to improved GOI characteristics.

Breakdown
The charge-to-breakdown (QBD) characteristics under constant current stress (-0.1A/cm2 for 100 seconds on 100x100µm NMOS capacitors) are shown in Figure 6. Time dependent dielectric breakdown is associated with trap assisted conduction through a small area of the capacitor. Such charge trap sites can be created by the hard mask nitride layer. After the insertion of a thin WSix between poly-Si and WN, we see enhanced QBD characteristics compared with the other gate stacks. On the other hand, the W/WN/TiN/Ti/poly gate stack shows degraded QBD characteristics compared with the W/WN/poly gate stack. This characteristic is consistent with the increased hysteresis area of film stress. The stress-relieved gate oxide resulting from a WSix inserted gate stack is believed to decrease defect generation from hard mask stress, resulting in improved QBD characteristics.

Interface traps
To better understand the different GOI characteristics for the different diffusion barrier metals, various other properties were also measured and compared on the NMOS capacitors. Firstly, Dit values were extracted by the conductance method. This can be derived from the conductance loss value (G/w) measured at voltages near Vth. A measured peak height corresponding to a conductance loss enables a Dit extraction by the following equation [7].

Dit = (G/w)max[ qfD(ss)A]-1

Where (G/w)max is the conductance loss at the frequency corresponding to the maximum peak value of conductance loss, ? is the angular frequency (w= 2p f, fis the measured frequency in the range 100Hz-1MHz), qis the electronic charge, fD is a universal function depending on the standard deviation (ss) of band bending, and A is capacitor area (4x10-4cm2). The fD value is 0.4 for the SiO2/Si system. After a constant current stress (-0.01A/cm2 for 100 seconds), we see conductance loss values for the WSix inserted stack below 3pF throughout the biasing range, which is the lowest value among the gate stacks examined. Similar characteristics are also obtained from J-V measurements. Gate oxide SILC was monitored at a gate voltage of -4.9V. We clearly observe that the WSix inserted gate stack shows less degradation in SILC. Figure 7 shows both gate oxide leakage current and Dit after electrical stress. The WSix-inserted gate stack shows lower SILC and Dit levels than other gate stacks. Due to the decreased Dit level with the WSix inserted gate stack, we can expect increased electron mobility with reduced coulomb scattering in the electron channel.

Oxide trap densities were measured by integrating the C-V hysteresis area after stress. The C-V hysteresis was measured from the inversion state to the accumulation state and back to the inversion state. There exists no hysteresis before the electrical stressing. The C-V hysteresis behaviour is known to mainly stem from the electrons which remain in the oxide traps near the interface during the C-V measurement, because the oxide traps near the interface have a longer time constant than interface traps [8]. With the help of WSix insertion, we obtain reduced C-V hysteresis and decreased flat-band voltage shifts, which result from the amount of electrical stress induced slow and fast oxide trap charges, respectively.

Transistor properties
To investigate the properties of transistors, the Id-Vg and Gm characteristics were measured for NMOSFETs with 10x10µm active area before and after Fowler-Nordheim (FN) stress (10MV/cm). Figure 8 shows the transconductance measured at the source-drain voltage of 0.1V. The WSix inserted gate stack revealed better stress-immunity in saturated drain current and transconductance (Gm) than other gate stacks. This improvement in FN stress immunity of the transistor is considered to be caused by the decreased Dit value. To investigate the physical properties of the different barrier metals, we conducted TEM and SEM analysis.

Figure 9 describes the cross-sectional TEM images of several gate stacks. Thin amorphous layers are observed between W and poly-Si for the W/WN/poly-Si and W/WN/WSix/poly-Si gate stacks. However, Figure 9c shows that the W/WN/TiN/Ti/poly-Si gate stack has no interfacial layer except for the Ti/TiN between the W and poly-Si.

Contact resistance
In order to compare the interfacial physical properties for the WSix and Ti/TiN inserted gate stacks in detail, we observed the top surface morphology by using SEM after stripping of Wlayer with hydrogen peroxide (H2O2) and a sequential dipping of the samples into a diluted selective poly-Si wet-etch chemical (HNO3:CH3COOH:HF:H2O in the ratio 50:25:1:50), which is very effective for the identification of dielectric layers formed on poly-Si or silicide. The poly-Si layer was hardly etched for the W/WN/poly-Si stack. This implies that a dielectric layer such as SiN is formed between W and poly-Si which prevents the poly-Si from being etched. On the other hand, in the case of the W/WN/TiN/Ti/poly, we see a reduced height of the remaining poly-Si after the dilute poly wet etch. This fact shows the non-existence of an interfacial dielectric layer.

In the case of the WSix inserted gate stack, we can observe some pin-holes formed due to etch-off of WSix and poly-Si layers. Accordingly, the thin interfacial layer on the WSix of W/WN/WSix/poly-Si gate stack is considered a metallic WSiN layer which is known to be a good diffusion barrier [9]. This WSiN layer may be a mixture of WSix and SiN.

The pinholes that were observed after the dilute poly etch, could be agglomerated WSix grains resulting from post thermal treatment. The other regions showing unetched poly-Si may have more SiN content in the WSiN layer that block the etching of poly-Si.

The partial reduction of the SiN dielectric layer could also contribute to the decrease of contact resistance between the W and poly-Si as for the W/WN/TiN/Ti/poly stack.

To compare the gate contact resistance value of various diffusion barrier metals, we measured specific contact resistance (Rc) using the Kelvin 4-probe method. Kelvin Rc was measured under the forcing current of 50µA. We observed that the insertion of WSix or Ti/TiN leads to one order of magnitude lower contact resistance values than for the W/WN/poly-Si stack. Also we find that the Ti/TiN inserted stack shows somewhat lower values than that of WSix insertion owing to the non existence of a SiN dielectric interfacial layer between the barrier metal and the WN, which is consistent with the results of the previous physical investigations.

Candidate for future gate stacks
Having studied the effects of insertion of WSix and Ti/TiN diffusion barriers between WN and poly-Si on gate oxide reliability and interfacial properties, we find that the W/WN/WSix/poly-Si gate stack shows the best gate oxide reliability among all gate stacks evaluated. This improvement is attributed to the stress relief from the inserted WSix film. Additionally, WSix insertion effectively reduces dielectric formation between W and poly-Si layers, and thus decreases the W-poly gate contact resistance. Therefore, W/WN/WSix/poly-Si gate stacks could be a promising candidate for future gate stacks in DRAM applications that require both good reliability and high speed characteristics.

References
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