Apache and NEC Electronics address (SiP) challenge
As part of the partnership, Apache and NEC Electronics have developed a methodology based on Apache's SoC power solutions and NEC Electronics' expertise on SiP design and technology.
As designs move beyond 90nm, understanding the impact of dynamic power noise on system behavior becomes a key requirement, especially for SiP designs where multiple integrated circuits (ICs) are placed in a single package sharing a common substrate.
Through an accurate representation of the IC's power network and switching noise, SiP designers are able to gain a more accurate view of the systems' power delivery, thus allowing them to optimize their IC-Package-PCB designs.
"Identifying power related issues found in the high-end SiP after silicon tapeout is both technically challenging and very expensive," said Akira Denda of Department Manager, Full Custom ASIC Division, 1st Systems Operations Unit, NEC Electronics.
"We selected Apache as our partner in addressing the power issues early in the design phase, as they are the market leader in dynamic power solutions and have a solid understanding of power noise related issues."
"NEC Electronics' experience in design and productization of SiP for various applications provided us with a good understanding of SiP design and analysis requirements," said Andrew Yang, CEO of Apache. "We are pleased to partner with NEC Electronics in jointly developing new solutions to address the power integrity challenge for package and system engineers."