Fab Management

quick cycle long spin
Minimizing on cycle lengths can have a dramatic effect on market share when bringing new IC’s to market. J. Blanc and S. Hury of INCAM Solutions France discuss how queue jumping may be the clue to achieving shorter cycle times by conveying rush lots in single wafer carriers.

Single Wafer Carrier can speed rush lots

Reducing cycle time is a key component of any fab manager’s task. J. Blanc and S. Hury of INCAM Solutions, France along with P. Vialletelle of Alliance Crolles, France explore the methods that ensure that rush lots of wafers do not get caught in the normal manufacturing process. This discussion charts their findings on improving rush lot times by simulation focus of single wafer carriers in the Back End Line of a fab.

Cycle time reduction is a recurrent goal for any Fab manager since being able to produce rapidly, new IC is a key to markets share increase. On present Fab architectures, different management solutions are used to help in completing these goals. For example, priorities in queues in front of equipment allow rush lots to achieve shorter cycle time than standard lots. Sometimes, equipment is reserved in advance so that rush lots don’t have to wait in front of them. Thus, a lot of effort is spent in reducing cycle time for critical wafers. Another wellknown solution is the lot size reduction which is also used in few fabs. Nonetheless, this strategy has never been applied completely since a lot size of one has never been used.

Therefore, the first idea developed in this article is to test the possibility of carrying rush lots in single wafer carriers. This point of view is experimented thanks to a dynamic and stochastic simulation of the Back End Line of a Fab. The second scheme consists of introducing suitable assumptions in the model previously created, in order to quantify the benefits and drawbacks of a full single wafer Fab scenario.

The model of a FAB BEOL
Generalities:
To write a model and run simulations, some elements have to be defined. The goal is the first concept to be characterized. According to this definition, the system is then analysed and some specific variables are set up: the inputs and the outputs. Inputs are variables used to change the conditions of the system and outputs are variables observed and used to compare these different conditions.

Regarding the model, our studies deal with the Back End Line flow, composed of more than 220 elementary steps processed on 28 groups of process tools. These groups can count up to 6 machines and all the process flow represents 14 mask layers. Therefore, wafers go through these groups several times: up to 45 times on some metrology tools and up to 23 times on one of the batch tools.

Assumptions on equipment
Some assumptions have been made in order to simplify the model and to better apprehend the complexity of the existing pilot Fab which data was used. Thus, only three types of equipment were considered and for each, the only available data was the maximum throughput (capacity of the equipment). Moreover, flows with different lot sizes (number of slots per carrier) can be introduced in the model. So, it has been necessary to link the Time of process (hour) to the Throughput (wafers per hour) and the Lot size (number of wafers in the carrier) as a function of the class of equipment. To answer this purpose, various simulations were run. Figure 1 plots the evolution of the capacity lost for each type of equipment versus the size of carriers used and shows clearly that each type of equipment behaves differently as a function of the number of slots per carrier. Consequently, the following required relations were determined:
● Single Tool: for this category, the equation describing its way of working is the following one:

Transfer time (hour) is the time to open the door and scan the wafers.
● Cluster Tool: for this category, 2 equations describe the way of working :
For FFOs (1 wafer)

For FOUPs (25 wafers)

Throughput loss is a percentage of capacity loss on the equipment when using only FFO.
● Batch Tool: for this category, all batch tools were assumed as 25 wafers internal cassette capacity. So, whatever the lot size (1 or 25), the equation

describes the way of working as the following:

Failures for each tool were also implemented based on their active time. Moreover, for some equipment, other flows such as “engineering” were taken into account thanks to a second type of failure that reduces the uptime of this equipment and consequently the average capacity.

General assumptions
It is assumed that the interfacing of FFO on equipment is exactly the same as the one on FOUPs which means that no extra time is necessary for the FFO to be locked on the Load Port. Only one process flow is considered for the whole mix (single product hypothesis), a recipe for 120 nm technology. It means that all the FOUPs or FFOs follow the same sequence process.

To take into account the uncertainty of transport (some failures may appear on conveyors), a random time of transport between each process was implemented. Therefore it takes around 10 minutes, varying approximately between 3 and 15 minutes to go from one place to another.

Wafer carrier rush lots
Specific conditions of the study:
For this study the goal was to quantify the impact of carrying rush lots in single wafer FOUPs, two main inputs were defined:
● the share of rush wafers carried in FFO.
● the batch rule which is the maximum number of FFO that are grouped together in front of the batch tool (as soon as this number of FFO is reached, the batch is launched for processing).

Regarding the outputs, 4 variables were identified:
● the throughput (wafers per hour),
● cycle times of FOUP and FFO ( per hour),
● Work In Process (number of wafers present in the Fab at the same time),
● number of Moves per hour (a move is a transfer of a carrier between any two load ports).

Moreover, it has been chosen to run simulations at the currently used level of 80% of capacity utilization of the BEOL of the Fab. For Rush lots carried in FFO, a priority was set up that enables them to be taken first from the queue in front of the equipment.

Results
Figures 2 and 3 introduce respectively the evolution of the throughput loss with a comparison of the cycle time of FFO and the cycle time of FOUP. Table 1 introduces the value of the WIP (Work In Process) and Move per hour for each case. The first point to observe is that of a batch rule of 2 and share of wafers with FFO higher than 15%. A forbidden zone appears where throughput is lost and cycle times skyrocket. In this zone, the loss of throughput generated by FFOs on batch tools is too high and a bottleneck appears. This creates up to 20% of loss of throughput, referring to figure 3 and table 1, it also makes diverging the average Work In Process, the number of moves per hour, the cycle times of FOUP and FFO.

On the contrary, for a batch rule higher than 2 and a share of wafers in FFO lower than 15%, single wafer logistics is completely viable. Moreover, an optimization can be made to find an effective zone where the cycle time of FOUP doesn’t increase and the cycle time of FFO is at its minimum. This region is defined by a batch rule of 3 and a proportion of 10 % of wafers carried in FFO. In these conditions, it appears that the cycle time of FFO can be more than twice less than the cycle time of FOUP. The AMHS has to be able to convey 3.5 (five) times more boxes per hour than before as well as managing up to 600 moves per hour. In summary, carrying rush lots in FFO allows a cycle time twice as less than the cycle time of a standard lot without modifying the performances of the Fab. Although it inflates the required capacity of the AMHS, it does so in a realistic range.

Projected full single wafer FAB
Specific conditions of the study:
The goal of this study is to quantify the performances of a single wafer carrier logistics. Only one input was defined: the capacity utilization of the full single Fab.

The outputs are the same as the previous study:
● the throughput (wafers per hour),
● cycle times of FOUP and FFO (hour),
● Work In Process (wafers),
● number of Moves per hour (a move is a transfer of a carrier between any two load ports).

The precedent results highlight all the problems related to the single wafer FOUP logistics in an existing model of Fab designed for a 25 lot size granularity. Thus, batch tools become a bottleneck if combined with the use of FFO. Cluster tools lose up to 40% of their capacity if combined with FFO and Automated Material Handling Systems need more capacity when wafers are conveyed alone.

First of all, in more and more Fabs, batch tools are replaced by single wafer tools since they allow a better control of the process and cycle time improvements.

Secondly, analysis on cluster tools highlighted the influence of the number of Load Ports in the loss of throughput of the tool when using single wafer carriers. These simulations also underline the possibility of changing existing cluster tools with three load ports into cluster tools with 9 “cat doors” (specific load port for FFO) to prevent losing throughput. So, it is assumed that if these cat doors are added to the tools it could set Throughput loss equal to zero highlghted in the equation (2).

Regarding the AMHS, FFOs have different advantages: it is lighter than a FOUP and the wafer is blocked in the carrier. Consequently, it can be projected that FFOs can convey wafers twice faster than FOUPs. Therefore, the third additional hypothesis is to make the average time of transport between each step equal to 5 minutes varying from 2 to 10 minutes.

Results
Figure 4 plots the evolution of the cycle time versus the capacity utilization. Two curves are plotted, one for the existing Fab and the other for the ideal single Fab. Table 2 introduces respectively the throughput, the WIP, the number of move per hour and the average cycle time (in days) per mask layer for each case.

The first and most interesting result is about the Cycle Time. Figure 4 shows that at 80% of capacity utilization the cycle time can be divided by 3.8 for all the production when using only FFO in an ideal single Fab.

Another interesting result is the average WIP (in terms of wafers) observed. Table 2 shows clearly that the WIP is divided by 3.8 thanks to the use of FFOs in a prospected full single wafer Fab. Moreover, table 2 indicates that the average throughput is the same for the two scenarios: in the existing and the ideal Fab. These results in terms of WIP, throughput and cycle time are then consistent since they verify the Little’s law. The result in terms of WIP is all the more important since, economically, a reduction of the WIP means a reduction of immobilized investments.

In the predicted single wafer Fab, a WIP of 320 wafers is observed contrary to a WIP of 1 200 wafers in the existing Fab. That means respectively 320 FFOs against only 48 FOUPs. So it will be necessary to have 6.5 times more carriers. Nonetheless, in terms of storage volume, 8 FOUPs are equal to 44 FFOs. So, nearly no more volume will be necessary in the full single Fab for carrier storage.

The last point but not the least is the number of moves per hour. Indeed, as explained before, the capacity of the AMHS was assumed as infinite. But, in order to have information on the capacity needed to get the results, the variable shown in table 2 (Maximum moves per hour) was implemented in the model. It appears that the full single Fab requires an AMHS capable of treating an average value of 1200 moves per hour. But it also has to be able to treat up to 2400 moves per hour. Therefore, a suitable handling system can be designed to answer to the requirements of the single Fab conceptualized in this article.

Different ways of using the FFO were tested in this article. It appears clearly that in existing Fabs, the FFO can only be used for rush lots (a low share of wafers in FFO) because of the existence of batch tools. On the contrary, the full single Fab projected looks like a real answer to the cycle time reduction goals. Indeed, it was highlighted a cycle time for all the production divided by around 4 as well as the WIP and however 6.5 times more carriers are needed, no more storage volume is necessary. At last, using single wafer carrier also has qualitative interests like a complete wafer to wafer traceability and cross contamination reduction.

The single wafer carrier Fab concept introduced in this article paves the way for designing express Fabs and looks like an important stake for all European Fabs that produce high added value ICs. In competition context between manufacturers but also between sites (Europe vs Asia), single wafer logistics sounds like a competition key for IC manufacturers.