Design for Packaging

Effective chip packaging starts with design

Historically there has always been a gap between designers and manufacturers in IC fabrication. With the growing challenges required to continue shrinking devices while increasing functionability the industry has seen the gaps along the manufacturing chain decrease with the need for a collaborative approach. Andy Longford of P&A Europe discusses how future packaging must begin in the design phase.

The explosion of semiconductor chip packaging in the last few years has seen many new and varied options of BGA, QFN, CSP and now wafer scale package technologies being developed to meet the ever demanding need of the industry for smaller, faster and cheaper products. However faster is not necessarily cheaper or smaller, often rather the opposite, and smaller is not necessarily faster or cheaper. In fact to get an effective package for today’s high performance chip devices, it is absolutely necessary to consider the style, choice and effect of the package upon the chip, right at the chip design stage.

Gone are the days when the chip designers can ‘throw their product over the wall’ to the assembly houses and expect to get back a correctly functioning packaged product. The process of housing a chip in a package or even directly to the board creates many new stresses, strains and parametric discontinuities that can often prevent the chip ever actually working to the specification for which it was designed.

Back end manufacturing
Typical “back end” manufacturing, that is assembly and test processes, have been assimilated in offshore regions of Asia- Pacific and now China, originally for cost reasons but now also for technology reasons. Here the “SATs”, sub-contract assembly and test houses, dominate the chip packaging industry and have formed relationships with the wafer fabs and foundries, in order to keep volumes flowing and prices competitive. Yet they are not developing new packages. They are relying upon trusted JEDEC standard types to meet market needs.

The bigger SATs players, such as AMKOR. ASE, CHIPAC etc., have been, to a limited extent, responsible for the development of chip packaging technology because they have become the total service suppliers. However, the bigger issues of application matched package designs are beginning to emerge with new demands for products in Radio, MEMs and Optical applications, where the package technology is being developed for specific and often smaller volume applications. The SATs have told their customers that they cannot afford to do the future package development, as they are being pushed to keep costs low. They do not have the capability to invest in the skills required to do all design and analysis without any reward. And why should they, when their customers will pay millions of dollars for a chip design but expect to get their package design for free. Markets in which European companies (such as Nokia) lead in terms of global innovation, are the Automotive, Telecoms, Transport, Defence and Aerospace segments. Here, the use of “standard” back-end package technologies has often not provided the best solution for many of the application specific, ASIC and system module electronics that have defined the electronics used in these industries. So the Indigenous Semiconductor device makers (IDMs) have been building up inhouse expertise in packaging, focussing on advanced packaging technology, to ensure they keep abreast of market demands.

These developments have really come about from the convergence of PCB and SMT technologies with traditional Chip packaging technologies. (See Figure 1). So much so, that packaging for the advanced technology applications currently being developed in Europe is moving ahead of traditional back end to the new paradigm of Chip Mount Technology (CMT). New processes, new machinery, new materials and new ideas are developing to match CMT expectations.

System in Package (SiP)
The outcome of the recent IMAPS UK MircoTech conference was that Design, Manufacture and Test for System in Package (SiP) Technologies is creating a demand for package complexity that will shortly match that of the chip itself. This offers either a very big warning, or a very big opportunity to the Microelectronics (and Nanotech) Industry. Co-design of chip and package is now a crucial need for advanced microelectronic systems, to ensure optimum functionality on a cost effective platform.

It was evident from the presentations by a number of the leading experts in the field of micro engineering that SiP products are now providing solutions for all high-tech electronic product designs, such as Ipods and mobile phones. However the packaging industry is claiming that it can only meet the challenges posed if the package and the chip are designed to work together. System in Package (SiP) and System on Chip (SoC) are directly related and can be combined in any ONE Package to produce enhanced functionality and performance at optimised cost. In addition there is no one unique packaging solution for every application and so choice of solution will depend upon the product requirements and best design achievable. SiP is the realization of the multichip package dream .(ref 1). The mobile phone has become the volume enabler for the SiP market. Many SiPs combine SoC to deliver increased functionality and performance in small form factor, resulting in significantly greater adoption rates than any previous multichip module. A variety of SiP constructions are shipping in high volume today, including stacked die, planar constructions with integrated passives, and stacked packages (see figure2). Yet very few companies understand just what the impact on chip performance is, when combining multi-functions together in one package. The object of SiP is clearly to bury the complexity in the package and keep the system design clean. (ref 2). The use of CAD tools is becoming increasingly the only way to enable the mounting of chips and interconnections in package modules. For SiP applications, it is becoming absolutely essential to emulate the performance of the packaged module in order to ensure that the chips will actually function in the way they were designed to do. Such design can now be likened to exactly that of using IP building blocks and interconnecting those in a typical IC design.

Roadmaps
Packaging and Assembly technology is a key segment of the International Roadmap for Semiconductors (ITRS). The 2005 edition states that Packaging is a limiting factor to performance for electronic systems and that assembly and packaging innovation covering design concepts, packaging architectures, materials, manufacturing processes and systems integration technologies are all changing rapidly. (ref 3). The need is to meet the challenges of Moore’s Law scaling and beyond in 3 dimensions.

Reviewing the ITRS roadmap and other roadmaps such as IPC, iNEMI and Jisso, they all highlight the fact that future packaging is going to be much more than a chip in a package. ITRS is essentially a roadmap for SiP applications as it has fully embraced the convergence of PCB technology and chip interconnect technology. Wafer Scale (WLP) of these systems is now being applied to board manufacturing, in order to keep cost down and productivity up. The logical development is, at last, beginning to emerge for chip packaging. The complexity of substrate design and verification depends upon the high level of integration between IC’s and their packages, such that packages are now the critical link.

The emerging demand for CMT will enable the package to be removed, revised, reduced or re-designed to suit matching the chip to the system need. The most effective “package” is potentially the SiP, which incorporates a number of IC’s embedded passives, power line protection and interconnection all into an integrated substrate that must itself be co-designed and co-verified, by software based systems. This ensures cost effective yields because it allows design optimisation of system performance, considering parameters of timing, signal integrity, input/output rules (for FPGA’s etc) and thereby can reduce PCB layers, number of external I/O and ultimately reduce onward manufacturing costs.

However, as chip designers know, such software tools are expensive and sophisticated. Additionally a whole new set of parametric standards are still required to ensure correct match of devices to package materials and assembly processes. Additionally FEA tools have to be developed to work out thermal and mechanical stress areas that can degrade performance and ultimately reliability. Such will be the demand of the new applications that many of the software design companies are now responding to these challenges and there are a significant number of research activities being funded to provide the necessary data.

The grand challenge
In the 2004 edition of ITRS, one of the “grand challenges” was stated to be that of ‘chip and package co-design’. This has now been replaced in the 2005 edition by a need to ‘Meet the challenge of cost and performance requirements of the market’. Cost has always been and will remain the major challenge for industry, yet put this way, it does not really focus the need of industry for the most effective package technology. Cost alone will often prevent achieving the package solution that matches and enhances performance requirements. So the most effective package has to be the one which meets cost and performance targets. It should therefore be understood that chip and package co-design is the critical function necessary to meet the latest ITRS challenges.

Conclusion
Future products will be more and more enabled by the use of micro/nano-devices and micro/nano-systems, spanning all areas of application and opening new business opportunities. Not only downscaling from existing products to smaller systems and components but also new concepts as well as the integration of the emerging field of nanotechnology and the micro-world will shape our future in an unprecedented way. To effectively package devices into systems is requiring a great deal of engineering which can only be successful if designed into the system, from conception to production. The cost of success will no longer be immaterial, it will be a significant percentage of the design.

REFERENCES
E.Jan Vardaman, TechSearch International Inc., New Drivers for Growth in SiP, IMAPS UK MicroTech conference, Cambridge UK , 7-8 March 2006.
A Fontanelli, P Viklund, Mentor Graphics, Design Challenges and Tools for System-in-Package applications, IMAPS UK MicroTech conference, Cambridge UK , 7-8 March 2006.
2005 ITRS – Assembly and Packaging Roadmap.
A Holland, CSR plc., Wafer-Level Packaging and Wireless Communications NMI, EPPIC Faraday
Wafer level Packaging Seminar, TWI Cambridge UK , 27 June 2006