ARRM 2006

IMEC maximizes its potential towards ‘More than Moore’

IMEC announced that it will give momentum to its ‘More than Moore’ research, building on its 130nm CMOS base process and expertise in heterogeneous technologies. Using its existing 200mm infrastructure, IMEC will offer CMOS-based process R&D combined with additional process modules and devices and application-specific demonstrators for ‘More than Moore’ processes and systems. Combined with its ‘More Moore’ research focusing on (sub) 32nm CMOS scaling in its 300mm clean room, IMEC is well positioned for collaborative nanoelectronics research for the next 10 years.

To realize this, IMEC will bring its multi-disciplinary research into a single operational scientific entity, starting January 1st, 2007. The scientific entity will be headed by Luc Van den hove, who will be promoted to Chief Operating Officer. The merging of the scientific divisions will enhance interaction between the different competences within IMEC, which becomes essential in an era where new technology solutions become increasingly application driven.

As an answer to this changing environment, IMEC will extend its R&D by combining conventional CMOS base processes (130nm/90nm) of IMEC’s 200mm pilot line with the integration of additional process modules and devices, and by developing application-specific demonstrators as proof of concept. All of this will be supported by dedicated design methods. IMEC’s 200mm pilot line with 130nm CMOS base process – 130nm CMOS generally considered to be the mainstream base technology for most of the ‘More than Moore’ research needs for the next 5 to 10 years - will be the cornerstone of IMEC’s ‘More than Moore’ research. Processes will be transferred to IDMs and foundries. IMEC’s facility will also be open to semiconductor equipment manufacturers, active in the ‘More than Moore’ area, in the framework of joint development programs.

In the field of heterogeneous technologies, IMEC has a lot of expertise regarding SiGe CMOS-compatible MEMS processing, above-IC RF passives and MEMS, sensors and actuators including biosensors, GaN on Si, silicon photonics, neuro-electronic devices etc. These technologies, combined with IMEC’s CMOS processing and advanced packaging technologies, will open up many new applications.

“With this reorganization, we will further develop critical mass in both ‘More Moore’ and ‘More than Moore’ research areas and ensure that both research domains are sufficiently integrated and interlinked,” said Gilbert Declerck, President and CEO IMEC. “Our successful core partnership program on (sub-)32nm scaling will proceed at the same level in our 300mm clean room.

IMEC demonstrates double patterning immersion litho for 32nm node

IMEC showed in collaboration with ASML the potential of double patterning 193nm immersion lithography at 1.2NA for 32nm node Flash and logic. These results prove that double patterning might be an intermediate solution before extreme ultraviolet (EUV) lithography and very high NA (beyond water) 193nm immersion lithography will be ready for production. Meanwhile, installation of both ASML’s XT:1700i immersion scanner and EUV alpha demo tool (ADT) runs at full speed in IMEC’s 300mm clean room.

Very promising double patterning results were obtained by splitting gate levels of 32nm half pitch Flash cells as well as logic cells in two complementary designs. The splitting was done automatically using software from EDA partners in IMEC’s lithography program. After splitting, both designs received optical proximity corrections (OPC) and a classical lithography approach “litho-etch-litho-etch” was performed. Exposures of both lithography steps have been carried out on a XT:1700i at ASML.

These results prove that the XT:1700i 193nm immersion tool, which has a maximum NA of 1.2, can be extended beyond the 45nm node. Since both hyper NA 193nm immersion lithography using high-index liquids and EUV still require a lot of research, IC manufacturers welcome double patterning as a solution to continue their research on material integration for the 32nm node.

Although quite some development is required to bring EUV to production ready, EUV lithography is the preferred option for many companies for the 32nm half pitch node due to its extendibility to 22nm and beyond. Since the arrival of ASML’s EUV advanced demo tool (ADT) mid August, significant progress has been made in the installation. Integration of the system (including the projection optics box of Carl Zeiss and the EUV light source of Philips Extreme UV) has started.

ASML will work on the verification and qualification of the various sub-modules in the tool.

“We are convinced that our advanced lithography program will offer our partners early lithography solutions to continue CMOS scaling beyond 32nm”, said Luc Van den hove, Vice President Silicon Process and Device Technology at IMEC.

IMEC’s multimedia decoding shows record power efficiency

IMEC has developed a reconfigurable processor for video decoding achieving power efficiencies 6 to 12 times higher than state-of-the-art C-programmed processors. The processor was derived from IMEC’s C-programmable ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) using its corresponding compiler. It proves that ADRES and its compiler are very well suited for time efficient integration in future lowpower portable wireless multimedia devices.

The processor was developed to support multi-format MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions ranging from QVGA up to D1. Its functionality is demonstrated for 30 frames per second H.264/AVC video decoding at CIF resolution by means of an FPGA (fieldprogrammable gate array) implementation.

To decode CIF resolution video in real time, the multimedia ADRES processor is only used for 1/6 of its total capacity (50MHz), resulting in a simulated power consumption of around 17mW for an ASIC implementation. The result proves the high performance efficiency of ADRES requiring only one single ADRES processor for handling 30fps H264/AVC video decoding at for example VGA (50mW, 150MHz) and D1 (68mW, 205MHz) resolutions.

ADRES, developed in the context of IMEC’s multi-mode multimedia (M4) program, is a new type of power-efficient, flexible computer architecture template designed to cope with the challenges presented by multimedia and wireless baseband processing for future mobile terminals. For each application domain, a specific ADRES instance is generated from a generic architecture template and is customized to optimally support the required computation at minimal power. One of its unique points is that it combines state-of-the-art power efficiency with programmability in a high level programming language for a complete application, which is of primary importance for short time-to-market.

Current research focuses on the application of the ADRES processor in a multi-processor platform for multi-format video decoding and encoding up to HDTV resolution H.264/AVC.

“With this demonstrator, we achieved a very important milestone in our multi-mode multimedia program. It shows that the ADRES architectural template as well as the corresponding compiler are sufficiently stable and operational for transfer to support industrial product development;” said Rudy Lauwereins, Vice President Design Technology for Integrated Information and Communication Technology at IMEC.This result was achieved in collaboration with IMEC’s M4 partners Samsung and Freescale and with the support of Barco Silex, Barco’s centre of competence for microelectronic design.

FinFETs for analogue and RF applications potential

IMEC demonstrated the potential of FinFETs by developing fully operational RF circuits and amplifiers using FinFETs with 45nm physical gate length and a metal-gate high-k gate stack. For applications at relatively low frequencies (below 5GHz) that demand a high-gain, FinFET technology offers better circuit performance than planar bulk CMOS. The speed of FinFETs still has to be improved for applications at higher frequencies.

The intrinsic gain of 45nm bulk devices drops to values that make it very difficult to realize high-gain operational amplifiers. By contrast, FinFETs have higher intrinsic amplification thanks to a better control of the short-channel effects. With the current status of the FinFET technology however, the maximum cut-off frequency of FinFETs is only 100GHz, almost 3 times lower than with planar bulk CMOS.

This is due to the series resistance of the fins and the lower mobility at the sidewalls of the fins. As a consequence, FinFETs show good performance characteristics for circuits up to 5GHz, and even higher performance than planar transistors for lower frequencies.

To demonstrate the potential of 45nm FinFETs, IMEC researchers have realized the functional analogue and RF circuits using FinFETs with a metalgate high-k gate stack and transistors with a physical gate length down to 45 nm. A two-stage opamp with 50 dB gain and a 2-8 GHz tunable oscillator were designed, processed and successfully tested.

Future work will focus on increasing the speed of the FinFETs, by increasing mobility, decreasing the relatively large series resistances and/or decreasing extrinsic capacitors between gate and drain. A bulk FinFET option is explored in research.

“Scaling beyond 45nm demands significant changes in process modules such as gate materials and/or device structures,” said Luc Van den hove, Vice President Silicon Process and Device Technology at IMEC.

“An early assessment of the potential of the different options for their analogue/RF performance is needed to maintain a competitive position. Therefore, this research forms an important aspect within our sub-45nm CMOS research.”

IMEC’s Flexible air interface for wireless terminals ready for transfer

IMEC has validated the hardware implementation of its software-defined radio digital baseband - called flexible air interface - for nomadic terminals achieving power consumption comparable with dedicated solutions. The cost- and power-efficient architecture supports all radio standards from next generation cellular (3GPP-LTE) to high data rate WLAN-WiMAX-DVB (OFDM-MIMO-based).

The FLAI platform achieves very high performance at low power, proven by only 300mW power consumption for the next-generation standard WLAN IEEE 802.11n using 2x2 MIMO (multiple-input multiple output with 2 antennas at input and 2 antennas at output). Ultra-low standby power is realized using a digital front-end featuring an application-specific integrated processor, which supports efficient wake-up of the FLAI on the detected incoming signals.

VStation emulator-based validation of the platform was shown in a wireless multi-mode operation for WLAN and 3GPPLTE standards. The chip tape-out of the FLAI platform (10mm2 in 90nm CMOS) is scheduled for Q1 2007.

The flexible air interface (FLAI) was realized using an inhouse developed heterogeneous multi-processor systems-on-chip platform. An intelligent controller exploits the scalability and heterogeneity of the platform to enable minimal power for the different operation modes. Next to an ARM controller for MAC functionality and power management and the digital front-end processor to support low standby power, the FLAI platform also includes two processors for baseband processing and foreword error correction. These processors were derived from IMEC’s Cprogrammable ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) using its corresponding compiler. The FLAI comes together with a full design environment. This enables industrial partners to efficiently develop their proprietary wireless software-defined radio platforms based on IMEC’s architecture.

“With this hardware validation achieving excellent performance, our software-defined radio digital baseband is ready for transfer to the industry;” said Rudy Lauwereins, Vice President Design Technology for Integrated Information and Communication Systems at IMEC. “Our FLAI solution enables seamless connectivity for mobile terminals operating at limited battery power.”

The FLAI was developed within IMEC’s multi-mode multimedia program with the support of Barco Silex, Barco’s centre of competence for micro-electronic design, CoWare and Mentor Graphics.

Copper-Top interconnect technology development and transfer success

IMEC successfully transferred its Copper-Top (Cu-top) interconnect process technology to National Semiconductor’s production facility in Malacca Malaysia. The Cu-top technology is a low resistance, post-passivation interconnect module particularly suited for analogue and mixed-signal applications. It improves system-efficiency and results in a significant chipsize reduction of such semiconductor devices.

The Cu-top module can be added to any semiconductor product wafer for current carrying capability. The sheet resistance of the interconnect layer is much lower than today’s standard back-end aluminum (Al) interconnects, therefore, making the technology especially suited for analogue and mixed-signal applications where relatively large electrical currents are used.

The technology overcomes the resistive voltage drop and power-loss caused by the low conductivity of traditional interconnects resulting in a significant increase of the system efficiency. Cu top prevents the use of wide metal lines and hence reduces chip areas.

The key feature of this technology is the use of Cu plating in a photoresist pattern, allowing for a small line width to enable a high-density high-current interconnect layer. The contacts through the 2µm thick IC passivation have a diameter of only 3µm and have a very good contact resistance between the plated Cu and the underlying Al layer.

The Cu layer on the chip is protected by a 10µm thick polymer dielectric layer. This layer is photo-defined to clear scribe lanes and bonding pads. The Cu bonding pads are covered with an Al metallization to allow for testing and wirebond packaging.

The process development and technology transfer results from a three-year close collaboration between IMEC’s thin-film technology group and a team from National Semiconductor Santa Clara, California (USA) and Malacca.

After procurement and installation of new equipment in the National Semiconductor’s Malacca facility, the technology was smoothly transferred to NSC.

IMEC’s collaboration with National Semiconductor is currently being continued to develop a significantly thicker version of the technology, resulting in a further reduction of the sheet resistance and consequently a higher power performance of analogue circuits.