Interfacing

High-Speed Interface and BiCMOS: Moving Digital Content with Analogue

Multi-gigabit applications often require signal-integrity features, such as equalisation and boost, for reliable data transfer between the source and destination. Jeff Waters, Product Line Director, Interface Division of National Semiconductor discusses the technology behind the 25 picoseconds of jitter in its buffer and multiplexer family, enabling error free transmission

The Visually Connected World.
An engineer is sitting on a flight watching last night’s edition of “European Football Review” on his video iPod. The previous night, he logged on to uefa.com, downloaded the episode through his laptop to his video iPod. Real football showing at high resolution on a mobile device – quick, easy, inexpensive.

Outside of Salt Lake City in Northern Utah, a family of five enjoy their Sunday evening. The two parents are watching CNN while one of their teenagers watches a baseball game on ESPN. Their other teenager is on her laptop, downloading her latest college texts over the internet while watching a streaming music video. Their ten year old is on the phone with a friend who lives across the country in New York. High-definition television cable service, a 15Mbps data connection, and unlimited phone service - $90 per month, one provider, no lost frames or musical notes.

Underlying this impressive distribution of digital entertainment are bits – 1’s and 0’s that have travelled with near flawless precision over thousands of miles of rugged terrain.

Let’s take the engineer’s football game. The original bits are created in the processing of analogue images into digital signals in a high definition video camera. The bits leave this camera at a data-rate of 1.485Gbps and travel across 140 meters of coaxial cable to a mobile broadcast truck, carrying video storage and satellite transmission equipment. The bits are transported back to the broadcast studio and run across more meters of coaxial cable to a video switcher – it sends the data across coax cables to video editing equipment that will merge the bits with other graphics for images like the scoreboard. The bits are now sent back over coax cables to the video switcher and then routed again over coax cables to a local server. Within the server, the bits travel from PCB to PCB across backplanes at 3.125Gbps, until they cross a Serial ATA cable at 3Gbps data-rates to a storage device.

When the engineer clicks on the uefa site to download the video, the bits once again leave the storage device across the cable to the server, and then traverse over fiber optic cable through tens of routers and across hundreds or thousands of miles to finally make their way to the engineer’s laptop. It is then a short meter or two over a USB cable at 480Mbps to his iPod, (figure 1).

The Analogue Revolution
At every instant where the bits travel across cables, connectors, or even across printed circuit boards, the bits come under attack from noise – in many cases to the extent that they are nearly unrecognizable as to whether they are a 1 or a 0. This noise can come from cross-talk noise from adjacent data channels, impedance discontinuities from connectors, or return loss from receiving nonidealities in transmitting and receiving interfaces. Unless cleaned-up, this noise will result in higher bit-error rates, and poor quality video, audio, or data.

So, at the heart of the spread of content – the final arrival of the digital revolution and the connected world – is the technology that cleans up these bits as they traverse from source to destination. And, oddly enough, what enables high-speed digital signals to traverse the rugged terrain is analogue technology – and more specifically, high-speed interface integrated circuits. And underlying all of this enabling technology are bipolar transistors, invented nearly 60 years ago.

What is High Speed Interface?
Essentially it is the use of analogue technology to clean up the damage done to differential digital signals travelling at rates of gigabits per second and higher. On the transmitting side, there are products called buffers that will use techniques like pre-emphasis that increase the high frequency energy of bits - this is done in anticipation of the losses which will be found in the transmission path. On the receiving side, there are devices called equalizers, which use high-pass filters that complement the low pass characteristics of the cable and compensating for its attenuation effect. While equalizers and buffers are effective in reducing this noise (or jitter) in voltage levels of bits, they are ineffective at reducing jitter in the timing. Here clock-data-recovery devices are required to realign bits with the appropriate clock edge (Figure 2).

These building block products can be thought of as a signal conditioning toolkit, and drive some of the more aggressive high frequency analogue circuits in existence. Other high-speed interface products, like Serializers and Deserializers, utilize these same underlying building blocks. Still others, like clock interface products, employ very high frequency phase-locked loops with narrow loop filters that clean jitter on noisy clock signals. What they all have in common, is the need to remove as much noise as possible from very high speed signals with the lowest power possible.

BiCMOS vs. CMOS
High-speed interface devices put significant demands on process technology. As described above, the primary focus of these devices is to lower noise, and to do so on signals that are running in excess of GHz frequencies. CMOS transistors offer high input resistance, and are optimized for switching speed at low power and small area – this is what drives their dominance in digital circuits, where cost (i.e. area) and power take presidense. The downside of CMOS however is noise. In order to achieve high speed, very small devices are required which generate higher noise than their bipolar counterparts at the same power. This is acceptable for digital logic, but not for driving clean signals or recovering signals over a significant distance.

Bipolar is quite complementary to CMOS. While consuming considerably more power than CMOS, its primary advantages are its higher gain and higher signal to noise ratios that stem from its higher operating voltages and lower noise. Given the distinct demands of low power and low noise in high-speed interface devices, the process technology of choice at frequencies above 1GHz is BiCMOS – a process that enables both bipolar and CMOS transistors to be used in the same circuit. This allows circuit designers to use low noise, high speed bipolar where signal integrity is paramount, and smaller, lower power CMOS where it is not of such great concern.

Market-driven Process Requirements
A challenge of the BiCMOS process, that is also relative to the CMOS or bipolar process is the compromise that must be made optimizing CMOS or bipolar transistor performance. Optimal tradeoff can be very device dependent, and because of this, there is great leverage for high-speed interface circuit developers having in-house proprietary processes.

National Semiconductor has used bipolar, CMOS and BiCMOS process technologies for decades and is a long-time developer of ultra-high frequency circuits. Defining the right process for high-speed interface starts with understanding the demands of the end-market. Figure 3 shows the primary performance requirements for some representative applications.

In addition having as low power consumption as possible is a desirable element, although none of these applications are battery operated, lower power consumption means less heat generated, which enables smaller form factor and lower cost.

As an example, medical imaging applications require multi-gigasample analogue-to-digital converters to achieve the degree of resolution required in resultant images. For these converters to operate at their maximum resolution, they require ultra-precise clock signals that derive from clock interface devices filtering noise from crystal oscillators and system clocks. For example, an 8-bit 1-Gigasample converter requires a 1GHz clock with 1ps of jitter for it to achieve its full potential of 8-bit resolution. (Figure 4)

Circuit designers now translate these higherlevel application requirements into device level needs, and must work very closely with process architects to better understand the trade-offs. Smaller process geometries enable lower power consumption, smaller die sizes, and typically lower costs. They also enable higher frequency CMOS transistors. This is why for digital circuits, the smaller the process geometry is typically is the better creating speed at low power and less expense. From an analogue perspective, however, the smaller process geometries mean faster transistors, but they also mean noisier ones. The lower supply voltages that accompany smaller geometry processes mean poorer signal to noise ratios – for devices like the voltage-controlled oscillators in clock interfaces, this can have a significant impact on phase noise performance. Architecturally, they also lead to weaker electrostatic discharge (ESD) protection.

A good example of this is field programmable gate arrays, or FPGAs. Due to the digitally intensive nature and large size of these products, they are usually at the cutting edge of ultra-deep submicron process technology. While many of them support high-speed interfaces, like LVDS or CML, they tend to suffer from poor noise performance due in part to massive switching noise among adjacent channels. This tends to result in them being able to drive at lower speeds over shorter cable or backplane distances as compared to discrete analogue solutions. They also suffer from extremely weak ESD protection. While discrete interface products provide upwards to 15kV of protection, FPGAs typically are an order of magnitude lower.

For National’s BiCMOS8 process, the primary goal was to achieve high enough frequencies – which for National’s key markets was a target cutoff frequency of 50GHz - with the lowest possible noise and power. Given these priorities, the frequency/noise/power performance of the bipolar transistors was prioritized well ahead of other factors like die size or the power consumption of the CMOS transistors. Figure 6

Process Specifics
National’s BiCMOS8 process features 0.25um geometries – clearly this is not the state of art found in pure CMOS processes, which are as low as 65nm, or BiCMOS processes, which are as low as 0.13um. Given the goal, however, to achieve a 50GHz fT bipolar transistor with very aggressive signal-to-noise characteristics, and other robust interface-critical features like high ESD protection, this was the appropriate process of choice. Moving to a 0.18um process, for example, would have reduced the supply voltage to 1.8v (from 2.5v at 0.25um), and would have made phase noise requirements very difficult to meet, due to the adverse impact on SNR.

To maximize the frequency to power relationship, a number of industry-standard techniques were employed – but the true differentiation enabling capability came from a number of patented techniques developed internally. Like most high speed BiCMOS processes, BiCMOS8 employed Germanium as a dopant in the base region of the bipolar transistors. The Germanium dopant profile is graded across the base with the higher Germanium (Ge) content on the collector side of the base (see Figure 5). This has two positive effects. First, it creates a drift field due to the non-uniform dopant concentration, accelerating conduction band electrons across the base. Secondly, the narrow bandgap of Germanium relative to Silicon (0.55eV vs. 1.12eV respectively). The grading of the Ge concentration has the effect of grading the bandgap, creating a “quasi-electric” field across the base. This effect dramatically minimizes the transit time of electrons through the base region, having a positive effect on maximizing performance.

To further enhance frequency, however, additional processes were employed. The most common measure of performance for a bipolar transistor is cutoff frequency, fT, which is the maximum frequency the transistor demonstrates as useful (i.e. >1) current gain. Described by the following:
1/(2*p*fT)=(Cje+Cjc)*(kT/q)/Ic + tE + tB + tC
tE, tB, and tC are emitter, base and collector carrier transit times, which are proportional to the width of the emitter, base and collector layers. Cje and Cjc are emitter and collector junction capacitance, respectively; given that the emitterbase junction is forward-biased during active operation, the emitter capacitance dominates the collector capacitance. It is proportional to the dopant concentration of the base region.

To minimize emitter junction capacitance, a patented low-doped base spacer was employed to lower the dopant concentration of the base at the emitter-base junction. While this has a positive effect in reducing Cje, it does widen the base width thus creating the negative effect of increasing base transit time. To mitigate this, Carbon was employed near the base-collector junction. This had the positive effect of blocking the Boron in the base layer from diffusing deeper during subsequent processing (minimizing base width, and hence, tb) and making the base dopant profile very sharp, maximizing its slope and hence the drift electric field. Overall, the focus is on optimizing the vertical transit time of carriers and thus speed of the transistor rather than the horizontal geometry which is the focus of CMOS scaling.

All this resulted in the dopant profiling shown in Figure 5, leading to an extremely effective process for National’s latest high-speed interface products. These products leverage the high performance bipolar transistors for the low noise signal path while leveraging the CMOS transistors for low power logic and control.

Moving Digital Content
The promise of a visually connected world is upon us, and although applications like real-time videoconferencing from your home are far from pervasive, the technology is there today. And as video becomes ubiquitous beyond the television for devices like cellular handsets, laptops, iPods, and cell phones, it will arrive there on the back of state of the art silicon process and analogue high-speed interface devices that will clean up dirty digital signals and ensure that you won’t miss a frame of action from last night’s football highlights.