Cypress Adopts Mentor Graphics Calibre xRC
Mentor Graphics Corporation announced that its high-performance parasitic extraction solution, Calibre xRC, is being used by Cypress Semiconductor Corp. in production flows for 130-, 90- and 65-nanometre processes. Calibre xRC was used at Cypress on its 72 Mb SRAM, as well as other custom memory, microcontroller and clock designs. Calibre xRC was chosen for its demonstrated accuracy in analogue/mixed-signal ICs, and an open calibration flow that accommodates internal manufacturing processes.
"Our latest PSoC designs are targeted at nanometre process nodes requiring very accurate parasitic extraction to feed into our downstream simulation," said Andy Hawkins, vice president of Design Technology at Cypress. "Additionally, because many of our designs are mixed-signal, the combination of analogue and digital content requires a mixed methodology of flat and gate-level extraction."
"For nanometre designs, accurate simulation and analysis requires more than traditional resistance and capacitance. Designers need a post-layout silicon model that incorporates inductance, in-die variation effects, and efficient accounting of effects not captured in the device model." said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics.
Shrinking geometries and increasing design size in the nanometer era have enabled greater functionality on a single chip. But with the increased functionality comes new complexities that create more problems in the attempt to attain design closure. This requires an electrical representation of the chip that accounts for the actual physical design of its devices and interconnect; an accurate silicon model. Calibre xRC meets the demands of nanometre designs with a comprehensive approach to device and parasitic extraction to compose accurate silicon models enabling a large variety of post-layout analyses.
