SEMATECH to continue pursuing planar transistor scaling strategy,
Front-end engineers at SEMATECH will combine planar CMOS approaches with new channel materials to develop effective transistors for the 22 nm half-pitch technology generation – but will continue to investigate FinFET devices as an alternative approach.
This ongoing strategy has been solidified by inputs from the consortium's member companies and from a select group of industry experts at a SEMATECH-sponsored workshop held in conjunction with the recent International Electronic Devices Meeting (IEDM).
"It appears there is still enough life left in planar scaling for the nearer term, especially with the incorporation of Ge into Si devices, but that three-dimensional devices and associated design capabilities will be needed to realize FinFET technology in the near future," said Raj Jammy, director of SEMATECH's Front End Processes (FEP) Division.
