New Materials

Gate to big changes
The new gate stack structure is ready, for commercial implementation in the move to 45nm production in 2010, according to the Sematech research consortium. The dual metal/high-k gate structure also removes the obstacles for the 32nm node in 2013. However, some companies plan to beat this schedule, Dr Mike Cooke reports.

Dual metal/high-k dielectric gate structures for pMOS and nMOS transistors have been developed and built, ready for the next step in CMOS development according to Sematech, Intel and IBM. The ‘dual' metal description describes the fact that different metals are needed for optimum performance of the two types of transistor. CMOS logic is based on the combination of the two types to achieve high density and performance.

This is considered by many to be a much bigger change compared with the move to copper and lowk metal wiring from aluminium/silicon dioxide (SiO2) begun a decade ago. The metal gate is being used to replace polysilicon and the high-k dielectric replaces SiO2 insulation.

Material Integration
The pMOS and nMOS materials were successfully integrated into highly scaled CMOS devices that showed low threshold voltage (Vt) similar to conventional polysilicon/SiO2 devices, with ultra-thin equivalent oxide thickness (EOT) in the range of 1.0–1.2nm. The main new development is pMOS, since materials for nMOS gate stacks had already been established last year.

CMOS devices were fabricated with conventional gate-first, high-temperature processing flows, with no reduction to drive currents or other performance measures. Extraordinary measures, such as substrate counterdoping, were not needed for the demonstration devices. "Details of the new technology have been transferred to SEMATECH members and will be discussed in future professional settings."

It was surely no coincidence that the following day Intel and a consortium led by IBM made their own metal/high-k gate stack announcements. Both companies are members of Sematech, along with one of IBM's partners, AMD. IBM's other partners are Japan's Sony and Toshiba (not listed on Sematech's members web page).

Intel says that it is the "biggest change to computer chips in 40 years". The company is planning to be first into 45nm production, beginning in the second half of this year. The company demonstrated working processors using the 45nm metal/high-k process in January this year (2007). Intel is currently developing its 45nm process on 300mm wafers in Hillsboro, Oregon, at its D1D fab. Further, two new 300mm fabs are being built for the coming 45nm ramp: Fab 32 in Ocotillo, Arizona (Figure 1, production due to start in the second half of 2007) and Fab 28 in Israel (production to start in the first half of 2008).

SiO2 Gate Dielectric
Intel is replacing the SiO2 gate dielectric used since CMOS production began with a thicker hafnium-based high-k material (Figure 2), reducing leakage by more than 10 times. Intel's metal gate recipe is ‘secret', but the company does say that it will use a combination of different metal materials for the transistor gate electrodes. Reported metal/high-k gate improvements for Intel's 45nm process technology include more than a 20% increase in drive current, giving higher transistor performance. Conversely it reduces source-drain leakage by more than five times, thus improving the energy efficiency of the transistor. A company representative says that the process was developed independently of Sematech. She also believes that most other companies are at the stage Intel was at in its research in 2003, when it wrote up its first papers on the technology.

IBM reports that it has inserted the technology (Figure 3) into its state-of-the-art semiconductor manufacturing line in East Fishkill, NY, and will apply it to 45nm chip production starting in 2008. According to IBM, the new materials were inserted without requiring major tooling or process changes – essential if the technology is to be economically viable. Previous steps along the way have already been reported, e.g. for nMOS [Narayan et al, VLSI conference, session 22.2, i2006], where hafnium dioxide was the dielectric and group IIA and IIIB metal layers were used before depositing a TiN/polysilicon electrode stack. A "similar forthcoming venue" will be used to report a summary of its final achievement of pMOS stacks.

Gate Stack
The gate stack is the key component in the metal-oxide-semiconductor (MOS) transistor since it provides the switch mechanism for current flow between the source and drain terminals (Figure 4). By varying the potential voltage on the gate electrode, one can vary the amount of carriers in the channel – if there are many carriers in the channel an ‘on' current flows, if there are few carriers the current is ‘off' (ideally zero, but . . .).

However, since there is a potential on the gate electrode relative to the channel, one has the conditions for current flow through the gate electrode. This leakage degrades the transistor's behaviour, particularly for low power applications. Therefore, one puts an insulator (dielectric) between the gate and channel to cut this leakage off.

The SiO2 of the original CMOS implementation from the 1960s is rather convenient since the base material is silicon. As the transistor shrinks the thickness of the gate insulation layer needs to be thinner. However, anorexic insulation layers are less able to block leakage current.

This year (2007), according to the International Technology Roadmap for Semiconductors (ITRS) 2006 update, CMOS transistors would need a silicon dioxide gate insulation layer that was 11 Angstroms thick (1.1nm). A silicon atom has a