SEMATECH & TEL launch multi year project investigating 3D interconnect technology and high mobility channel materials in advance semiconductor manufacturing.
SEMATECH & TEL partner in 3D interconnect & high-mobility channel material
SEMATECH and Tokyo Electron Limited (TEL) have launched a multiyear joint development program aimed at improving the prospects for using 3D interconnect technology and high mobility channel materials in advanced semiconductor manufacturing.
These programs mark the beginning of a new collaboration in which SEMATECH will partner with leading suppliers to address key technology challenges that are important to semiconductor customers. This offers suppliers lower R&D costs, accelerated results in technology development, and more efficient and effective technology implementation into leading-edge production fabs.
Under agreements involving an exchange of intellectual property and funding, SEMATECH and TEL engineers will collaborate on two separate projects, one a three-year effort to transcend the barriers to 3D processing in volume manufacturing, and the other a two-year project to advance the feasibility of using silicon-germanium in transistor gate stacks to increase processing speed.
"Technical engagement with key industry suppliers has long been a core strategy of SEMATECH," said Giang Dao, vice president and COO-Advanced Technologies for the consortium. "TEL has been a valued partner for many years - and we're delighted with this opportunity to take our relationship to a new level as we launch two new advanced technology R&D programs."
Masayuki Tomoyasu, Director of Development and Planning and Chief Engineer for TEL, added:
"We are excited by this opportunity to join TEL's engineering expertise with SEMATECH's R&D capabilities and know-how to develop leading-edge 3D and epitaxial capability for our semiconductor customers."
Under the 3D program, SEMATECH and TEL will work jointly on early development challenges, including cost-of-ownership modelling, process benchmarking, establishing standards, technology roadmapping, and the formation of through-wafer silicon vias. Related to that work, TEL will tap into its extensive Si etch experience for high aspect ratio, high rate etch development capability at its R&D labs in Japan.
Etch tool upgarde
Additionally, TEL will be upgrading an existing low-k dielectric etch tool in ATDF, SEMATECH's subsidiary R&D fab. The upgrade will introduce considerable flexibility in understanding the etching of porous low-k materials and improve the process uniformity and capability of the chamber. These activities will support development of low-k materials for the 45 nm and 32 nm technology generations.
"3D technology offers the prospects of improved performance and functionality, reduced power and chip area, reduced development costs, and faster time to market over conventional, two-dimensional designs," said Sitaram Arkalgud, SEMATECH's Interconnect director. "3D also could allow chipmakers to heterogeneously integrate incompatible fabrication technologies into a single stacked system. However, all sections of the industry must come together to address the availability of the proper infrastructure. We are excited to have TEL as a key partner as we increase the scope of our 3D program."
Front end process
The second program will draw on SEMATECH's Front End Processes (FEP) and TEL engineers to pioneer the use of alternative epitaxial materials in transistor channels. Engineers from both companies will work together to develop processes and to integrate such materials with high-k metal gates on advanced short channel devices.
"This work will bring significant benefits to our members by refining our processes on epitaxial channels," said Raj Jammy, SEMATECH FEP director. "It allows us to develop new industry standard and manufacturing-friendly processes that can benefit member companies while giving us better insights into the technology."