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Power Management

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Comparing Avalanche or UIS Mosfets
Design plays a huge part when it comes to the effectivity of power management in device manufacturing. Alexander Craig, Fairchild Semiconductor discusses how good design planning can improve the reliability of power MOSFET components.

How to select and compare AVALANCHE or UIS MOSFETs


Chip designers have to consider where the devices they manufacture will end up, as there will be different power supplies. MOSFET specification and application within the circuit is one of the easiest ways a designer can improve the relability of power MOSFET components. By Alexander Craig, Fairchild Semiconductor.


The vast number of loads driven today are inductive in nature such as solenoids, transformers, inductors and so on. Power MOSFET (Metal Oxide Field Effect Transistor) failure due to Unclamped Inductive Switching conditions is one of the most prevalent failure modes encountered. Proper MOSFET specification and proper application of the MOSFET within the circuit is one of the easiest ways a designer can improve the reliability of their power MOSFET components. Different power MOSFETs from different technologies or suppliers that have close RDS(ON) (onstate resistance) and BVDSS (Breakdown voltage) values may have very different performance from an Avalanchei/UIS (Unclamped Inductive Switching )ii perspective.


Avalanche/UIS capability is a complex function of many different parameters largely dominated by die size but not exclusively. The EAS (Energy Avalanche Single Pulse)iii value itself as represented on most datasheets is NOT a good method for comparing UIS capability. Some devices are measured at the rated current and some at a fraction of the rated current. Some suppliers provide a lot of data on the UIS test and yet, some only provide the EAS value. Generally, the only common parameter is TJ(START) (junction temperature at the start of the UIS event) at 2500c. For this reason, comparing UIS capability can seem difficult. But a simple method exists to allow a fairly accurate comparison from datasheet specification.


Before getting into the Avalanche/UIS comparison issue, a brief review of the physics involved is in order. Modern avalanche rated power MOSFETs are designed to handle a certain amount of stress under an UIS event. This is basically when the device is forced to pass current usually stored in an inductor when off or turning off and a voltage generated by the inductor, greater than BVDSS is applied across Drain to Source. This condition is also known as avalanche. These devices have suppressed the parasitic BJT turn-on under this type of stress. In modern rugged MOSFETs, the UIS failure is thermally induced meaning that some part of the MOSFET gets too hot. As a MOSFET die gets hot, its breakdown voltage increases. This means that under an avalanche condition, the point that is the hottest will move around the surface of the MOSFET. This will help distribute the heat over the surface of the die. If the die is small, it will not take long for the total surface to get quite hot. The larger the die, the longer the part will survive in avalanche. If the heat generation is fast (a high current pulse), then the flow of heat away from the source may not be fast enough and the temperature will rise very rapidly. The obvious question is how hot is too hot. The answer is related to the epi doping concentration, Nd for an N-channel MOSFET or Na for a Pchannel MOSFET. The temperature that is too hot is not TjMAX (Maximum allowed junction temperature for safe operation), it is known as the intrinsic temperature.


As silicon heats up the background hole electron pairs also known as the intrinsic carrier concentration "ni" increases. Empirical data has shown that the relationship between ni and temperature follows Equation 1 for silicon.


ni = 3.88E16(T1.5)exp(-7000/T) cm-3 (T is in ºKelvin) Eq.1


Equation 1 shows that as the temperature increases the thermally generated carriers or ni increases. When these thermally generated carriers swamp the number of doping atoms, free carriers will exist. If an electric field is present this will form a current. When ni > Nd, for an N-channel MOSFET the doping is no longer having an effect and the silicon behaves intrinsically. Therefore the temperature at which ni = Nd is called the intrinsic temperature. In short when the temperature reaches the intrinsic temperature - the device will fail.


MOSFET designers adjust the epi resistivity (a function of Doping) and thickness to balance the lowest RDSon, BVDSS and Manufacturability. The relationships are as follows:
● High epi resistivity (lower doping concentration) will give higher BVDSS values.
● Low epi resistivity (higher doping concentration) will give lower BVDSS values.
● High epi thickness will give higher BVDSS values.
● Low epi thickness will give lower BVDSS values.
● High epi resistivity (lower doping concentration) will give higher RDSon.
● High epi thickness will give higher RDSon.


Therefore, for any given MOSFET design, a unique set of doping concentrations and epi thicknesses will apply. In general, the MOSFET manufacturer wants to minimise the number of changes from one breakdown voltage to another in a technology or cell design. The epi resistivity tends to be a primary variable for different breakdown voltage devices in a given technology.


Now back to Avalanche/UIS rating issue. As shown in Figure 1 the concept of constant energy avalanche capability is invalid. Note that the energy that the device is capable of handling is basically 2000mj and below, limited by Imax (maximum allowed drain current) with ~200A at the low end and the pulse at the high end.


With the concept of constant UIS energy, the relationship "IAS 2 α 1/L" from E=1/2LI2 would be expected to produce a slope of -1/2 when the failure loci are plotted in a Log-Log graph with the current IAS (Current (I) Avalanche Single Pulse)iv as the vertical axis and the inductance L as the horizontal axis. As shown in figure 2 avalanche capability as a function of L has a slope of -1/3.2 this is a relationship of "IAS 3.2 α 1/L" not "IAS 2 α 1/L". But by plotting the same failure loci on a Log-Log graph with the current IAS as the vertical axis and the time in avalanche tAV as the horizontal axis. A slope of -1/2 is seen. Thus a relationship of "KUIS=tAV*I2" exists. ("tAV" - Time in Avalanche)v Further study has shown that the results obtained on power MOSFETs, once the parasitic bipolar turn-on mechanism is suppressed, are similar to those obtained on rectifiers. Therefore the power MOSFET capability is that of its body diode. Figure 2 shows the difference between these two concepts by using the same failure loci for the same device plotted with two different horizontal axis.


With the above understanding to compare the UIS capability of different MOSFETs you need only know the breakdown voltage of the device (BVDSS), the rated avalanche energy (EAS) and current the avalanche energy was measured at (IAS). With these 3 bits of data and equation 2, a simple method for accurate comparison of different MOSFETs is developed.


Equation 2: EAS=0.5*(1.3* BVDSS)* (IAS)*tAV solving for tAV and rewriting tAV =(2*EAS)/((1.3* BVDSS)* (IAS))


By plotting the EAS point on a Log-Log graph with IAS as the vertical axis and tAV as the horizontal axis and projecting a line through the point at a -1/2 slop yields the MOSFET UIS capability at any allowed current. Figure 3 Shows how 7 different ~60V MOSFETs from 3 different suppliers with relatively close RDS(ON) used for the same application compared on a UIS perspective.


The 32 mohm, 39 mohm from comp "C" and 43 mohm devices all have roughly equivalent UIS capabilities since they lie on the same -1/2 slope line. But each was measured and rated at different currents and is listed at different EAS points on the Data sheet. For the 32mohm device EAS at 10A is 225mJ is used, the 39mohm comp "C" device EAS at 16A is 128mJ is used and the 43mohm device EAS at 10A is 214mJ is used.


Even more noteworthy is that the 39mohm comp "C" device listed EAS at 16A is 128mJ and the 39mohm comp "A" listed EAS at 32A as 350mJ. The UIS capabilities are quite different between these two devices but if one looks at the same IAS value since in the same application it is likely that both devices would see the same current using 20A at a target IAS, we see that from equation 2; EAS for the 39mohm comp "C" device is 101mj and that the 39mohm comp "A" devises EAS at 20A is 546mJ over 5X the capability.


In conclusion, given BVDSS, rated EAS, and the current at which the avalanche energy was measured (IAS), and using the formula EAS=0.5*(1.3* BVDSS)* (IAS)*tAV, one can plot the EAS point on a Log-Log graph with IAS as the vertical axis and tAV as the horizontal axis. By projecting a line through that point at a -1/2 slope yields the MOSFET UIS capability. Any point of operation above and to the right is outside the capability of the device. Any point below and to the left is within the capability of the device at a TJ(START) of 25oC. Higher TJ(START) values move the line down and to the left. This method allows fair accurate comparison of UIS capability of any avalanche rated power MOSFETs from different technologies or suppliers.


 


REFERENCES
(i) Avalanche; A condition when the drain-source voltage exceeds the bulk break down of the Power MOSFET.
(ii) Unclamped Inductive Switching; A context sensitive term used to describe a Power MOSFET's ability to sustain energy in the avalanche mode of operation or it can be used to describe a circuit which is driving an inductive load without a drain clamp.
(iii) Energy Avalanche Single Pulse; the level of energy that a part can dissipate in the avalanche mode for a single nonrepetitive pulse.
(iv) Avalanche Single Pulse; The magnitude of IDS that a part can sustain in the avalanche mode for a single non-repetitive pulse.
(v) Time in Avalanche; A term used in specifying UIS capability that signifies the amount of time that the device is in the avalanche mode of operation


 



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