Collaboration with Japan will develop new-generation analysis flow for IC design
Extreme DA and Semiconductor Technology Academic Research Centre (STARC) are collaborating to jointly develop and validate a variability-aware timing analysis flow for integrated circuits (ICs) manufactured in 65- and 45-nanometer (nm) processes.
At advanced process nodes of 65-nm and below, statistical analysis software is required for analyzing device mismatch and global variations. This analysis helps designers understand the impact these effects have on meeting timing targets for their IC designs. STARC has established the correlation between the Extreme XT timing analyzer and SPICE for 65-nm designs, and verified Extreme XT's suitability for the statistical optimisation of designs.
"We are committed to analyzing, testing, and delivering advanced tool flows to meet critical issues in manufacturing-aware design," said Nobuyuki Nishiguchi, vice-president and general manager of Development Department-1 at STARC. "Working with emerging technology companies like Extreme DA and bringing verified flows to our member companies is a key mission for STARC."
"I am pleased we are working closely with STARC to validate our statistical timing analysis. We believe the collaboration will result in increased adoption of our signoff timing solution by makers of advanced IC designs." said Mustafa Celik, president and CEO of Extreme DA.
