Singapore site mapped for next generation R&D facility
STATS ChipPAC has announced plans to establish a new research and development (R&D) facility located in Singapore which will be dedicated to developing next generation technology including through silicon via (TSV) and microbump bonding for three dimensional (3D) die, silicon substrate based packaging solutions, and embedded active die technology.
The new R&D facility includes over 10,000 square feet of Class 10, 100 and 10K cleanroom space with an additional 9,000 square feet of space available for future expansion. The R&D operation will specialise in wafer level processing with an equipment set for photolithography, plasma etching and deep reactive ion etching (DRIE), wafer thinning, and wafer bonding. A strong engineering workforce of 40 employees will focus on advanced wafer integration technology.
"As the semiconductor industry moves to finer pitch technology nodes to increase device functionality, performance and speed, there are technical challenges and performance limitations with standard packaging technology. How devices are stacked and interconnected has a significant impact on the size and performance of the final solution," said Dr. Han Byung Joon, STATS ChipPAC's Chief Technology Officer.
"STATS ChipPAC has taken a pivitol role in driving integration technology and flexibility in packaging architecture and we believe the next important step is to build on our 3D wafer level integration technology." Dr. Han continued, "The new facility fulfils an important role in the Company's global R&D strategy and will augment our current worldwide R&D operations focusing on advanced packaging solutions."
