Info
Info
News Article

Next-Generation Parametric Test Challenge Solutions

News
Next-generation semiconductor manufacturing processes and new process technologies have created many difficult challenges for production parametric test systems. Massive volumes of parametric test data are needed to insure the integrity of advanced semiconductor processes creating a near-crisis in terms of wafer throughput. Here, Alan Wadsworth,Marketing and Communications Manager, HSTD Division, Agilent discusses how to overcome these issues.

The pulse-generation needs for testing state-of-the-art flash memory cells have exceeded the capabilities of the current generation of parametric testers. The RF parametric testing needs for processes used to manufacture ICs for the communications industry present both calibration and throughput restraints. To overcome these issues, innovative new tester hardware and software solutions are required.

Architectural Improvements
Improving measurement throughput has been and continues to be the key challenge in production parametric test. Continuing reductions in process lithography have only exacerbated the throughput concern, since smaller device geometries generally require more measurements due to the greater potential for performance variations at the device level. This "variation" issue has been widely discussed in the industry as one of the barriers that must be overcome at and below the 45 nanometre level. Finally, the use of "technology boosters" such as high-k gate dielectrics and strained silicon necessitate more and different types of testing than in previous generations of silicon. Taken together, these factors mandate much faster test methodologies than have been used in the past just to keep parametric wafer testing throughput at current levels.

""

The simplest method to improve measurement throughput is to increase the measurement speed. Although the speed of some parametric measurements is determined by the physical limitations of the test structures, architectural improvements in the tester itself can reduce measurement times. In the case of the Agilent 4080 series, enhancements to the tester architecture coupled with digital circuit redesign including a faster CPU yield speed improvements of 10-20% on test plans transferred over from Agilent 4070 series testers. This has the advantage of offering an immediate boost to measurement throughput without having to make any fundamental changes to the measurement methodology or to the test code being executed. However, although faster measurement performance can help to solve some of the throughput conundrum, this alone cannot meet all of the performance requirements of advanced processes.

Overcoming Throughput Limitations
The most efficient means to boost measurement throughput without increasing the number of testers or tester resources is to use parallel testing techniques. If one or more tests at a time can be performed in parallel, then maximum use can be made of all available measurement resources on a per tester basis. While simple in theory, in practice the implementations of parallel testing to date have been limited in their effectiveness due to the complexities of realising truly independent parallel test architectures. Until now, all parallel testing schemes available for production test have been synchronous in nature; this means that all parallel measurements tasks currently running must complete before a new set of measurement tasks can begin. This
has the disadvantage of creating measurement "dead time" (time where measurement resources are waiting for another measurement task to complete). To adequately meet the production parametric testing challenges of advanced sub-micron technologies, improvements in the current parallel testing methodologies are required.

""

All members of Agilent's new 4080 series of parametric testers support a new Virtual Multiple Testhead Technology that supports true asynchronous parallel test, significantly increasing measurement throughput. This technology is supported under both the Agilent SPECS test shell and the SPECS-FA (factory automation) test shell. It is equivalent to having several test heads connected to a single tester. All measurement tasks run completely independently of one another. Each measurement task can start a new measurement as soon as it completes its current measurement, regardless of the status of the other measurement tasks. The SPECS software even has a Scheduling Analyser tool that permits the real-time monitoring of the parallel measurement tasks during production.

Parallel test requires a fundamental re-thinking of testing strategy and test structures in order to be effective. The test element group (TEG) used must be designed to permit the testing of multiple structures at once. This means that precautions must be taken to insure that substrate leakage currents do not cause the measurement of one transistor to affect the measurement of another transistor. Also, the distribution of the devices among the various test element groups needs to be optimized to take maximum advantage of tester resources. For example, MOS transistor measurements typically require four SMUs per device, which means that in general only two transistors can be measured in parallel at once (since the 4080 series supports a maximum of eight SMUs). However, the 4080 series also supports a high-speed capacitance measurement unit (HS-CMU), which permits the fast measurement of capacitor structures and functions independently of the SMUs. Therefore, for optimum throughput the TEG should be designed such that transistors and capacitance structures can be tested simultaneously. By careful design of the TEGs, asynchronous parallel test can yield throughput improvements of as much as 50% over conventional serial testing techniques.

In addition to asynchronous parallel test, synchronous parallel test can also provide significant throughput improvements under certain circumstances. The choice to perform synchronous or asynchronous parallel test depends upon the available measurement resources and the type of measurement to be performed. Synchronous parallel test works best when testing groups of similar devices (such as resistor structures) that do not require more than one or two SMU resources per measurement. For example, the Agilent 4080 series can synchronously measure up to eight resistor structures in parallel by utilising all eight available SMUs and the ground unit (GNDU). Again, careful planning of the TEG design up-front is required in order to optimise the throughput based on the available tester resources.

Solving Flash Cell Testing Challenges
The non-volatile memory market continues to be one of the most rapidly growing and dynamic areas in the semiconductor industry. In particular, the explosion in the NAND flash memory market, driven largely by removable flash storage cards and MP3 players, continues unabated. The computer industry goal of replacing the hard disk drive (HDD) with a flash-based equivalent will only continue to expand flash memory demand in the future. However, this market can continue to grow successfully only if the reliability of the flash cell can be assured. The variation issue previously mentioned has an especially significant impact on flash cell processing, requiring more extensive monitoring during production. Also, new flash cell technologies such as multi-level cell (MLC) and charge trap flash (CTF) need extremely accurate voltage pulse levels for correct characterisation. In order to guarantee reliability of the flash memory cell, a fast, accurate, and efficient means to test the cells in production is required.

The process of checking flash cell reliability is relatively simple. The test equipment writes and erases the flash cell structure thousands or hundreds of thousands of times, and then measures the threshold voltage (Vth) separation between the programmed and unprogrammed states. If too much charge gets trapped in the floating gate during the write/erase cycles, then the difference in Vth between the programmed and unprogrammed states of the flash cell can become almost the same. The net result of this Vth convergence is a functional failure of the flash cell, since the sensing circuitry of the flash memory IC will not be able to distinguish between a "0" and a "1".

Previous generations of production parametric testers have been restricted in their flash cell testing capabilities by the limitations of the pulse generator instrument units that they used. Off-the-shelf pulse generator instruments are not optimized for flash cell testing. For example, the write/erase requirements of NAND flash cell erasing generally exceed +/- 20 V and they also require flexible pulse edge control. In addition, many types of flash memory require tri-level pulse generation capability. The combination of these features is not available in off-the-shelf pulse generator instruments.

The Agilent 4082F Flash Memory Cell Parametric Test System is optimized to meet the parametric testing needs of modern flash cell processes. The 4082F supports a new highvoltage semiconductor pulse generator unit (HV-SPGU) that is specifically designed for flash cell testing. Each 4082F HVSPGUs has two channels that can supply +/- 40 V output (80 V peak-to-peak) voltage pulses. They can output tri-level pulses and they also have programmable rise and fall time control down to 20 ns. To meet the exacting needs of MLC flash cell characterisation, the HV-SPGU output level accuracy is 2% with voltage force resolution down to 0.4 millivolts. The 4082F can support up to five HV-SPGUs, for a total of ten channels. In addition, a high-frequency (HF) matrix option with up to 60 MHz bandwidth is available for use with the HV-SPGUs. The HF matrix can be configured as either two 3 x 24 matrices or one 3 x 48 matrix. The HF matrix allows the outputs of the HVSPGUs to be routed to any of the available output pins in the test head. This flexibility gives the 4082F the ability to meet the testing challenges of today's flash cell processes, as well as providing more than enough capability to meet any challenges that might arise in the future.

""

RF Testing Challenges
For processes used to manufacture ICs with high-frequency performance (GHz range), verification of the RF performance of the process on-wafer before assembly and final test is required. This need is driven by the fact that there is no simple means to correlate the DC measurement performance of devices with their RF measurement performance. However, on-wafer RF measurement creates many testing difficulties that do not arise with simple DC test. RF measurement equipment requires frequent (at least daily) calibration to maintain accuracy, and traditionally the complexity of this calibration has required engineering skill and knowledge. In addition, with no means to switch between different RF devices after contacting a probe card, the throughput of the RF testing has been a production bottleneck. Some solution was needed to make the RF parametric testing as simple and efficient as has been the traditional DC parametric test.

The Agilent 4083A DC/RF Parametric Test System solves these RF testing challenges through both innovative software and hardware. The 4083A system software supplies an interactive and automatic software calibration tool that is so easy to use that an operator can easily perform RF calibration operations such as SOLT and open/short de-embedding. The 4083A also has the industry's first RF matrix option for production parametric test. The 4083A's optional RF matrix has eight inputs and ten outputs, with 20 GHz measurement bandwidth. Since RF test structures typically have two ports, this permits the testing of up to five RF test structures in a single touchdown. Taken together, these capabilities permit the easy integration of RF test into wafer production facilities, without the need for extensive training on RF calibration or the need to sacrifice wafer throughput.

Summary
The Agilent 4080 series of parametric testers were designed specifically to meet the challenges of advanced next-generation semiconductor processes. They provide significantly faster throughput via architecture improvements that boost measurement speed, as well as both synchronous and asynchronous parallel test capability. They offer unprecedented flash cell testing capability via integrated semiconductor pulse generator units. They also provide easier RF wafer testing via innovative software and hardware capabilities. The uniform architecture of the 4080 platform makes it easy to upgrade from one platform to another if necessary.

The modularity of the system hardware also protects the user's investment by insuring that the test system does not become obsolete. The 4080 clearly meets the needs of both mainstream and advanced sub-45 nanometer processes, and it can also yield many performance and throughput advantages for current wafer fabs as well.



AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS
Cadence Announces $5M Endowment To Advance Research
Imec Demonstrates 20nm Pitch Line/Space Resist Imaging With High-NA EUV Interference Lithography
SUSS MicroTec Opens New Production Facility In Taiwan
TEL Introduces Episode UL As The Next Generation Etch Platform
Belgian Initiative For AI Lung Scan Analysis In Fight Against COVID-19 Goes European
New Plant To Manufacture Graphene Electronics
EV Group Establishes State-of-the-art Customer Training Facility
GOODFELLOW Confirms Membership In The BSI UK Graphene Group
South Korean Point Engineering Chooses ClassOne’s Solstice S8 For Advanced Semiconductor Plating
K-Space Offers A New Accessory For Their In Situ Metrology Tools
ITRI And DuPont Inaugurate Semiconductor Materials Lab
Will Future Soldiers Be Made Of Semiconductor?
U.S. Department Of Defense Partners With GLOBALFOUNDRIES To Manufacture Secure Chips At Fab 8
DISCO's Completion Of New Building At Nagano Works Chino Plant
Can New Advances In CMOS Replace SCMOS Sensors In Biomedical Applications?
AP&S Expands Management At Beginning Of 2021
Onto Innovation Announces New Inspection Platform
Panasonic Microelectronics Web Seminar
Changes In The Management Board Of 3D-Micromac AG
Tescan And 3D-Micromac Collaborate To Increase The Efficiency Of Failure Analysis Workflows
Tower Semiconductor Announced Program Creating An Integrated-Laser-on-Silicon Photonics Foundry Process
Siemens And ASE Enable Next-generation High Density Advanced Package Designs
Obducat Receives Order For Fully Automated Resist Processing Tool From A Customer In Asia
ASML Reports €14.0 Billion Net Sales

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification} Array
Live Event