Yield Improvement

Detecting Yield Limiting Electrical Shorts with E-Beam System in process Optimisation and Monitoring

The ability to capture killer defects in the contact layer using an e-beam inspection system was used to find the root cause for yield loss. Here Yan Li and Henry Chen of Semiconductor Manufacturing International Corporation, Beijing, China and Robbinson Liu and Frank Fan of KLA-Tencor China, E-Beam Inspection, describe how EBI helped to identify the root cause of an electrical short defect, a process issue, and improve yield through optimisation of process conditions.

Electron beam inspection (EBI), through the use of the voltage contrast (VC) effect, is used extensively in the manufacture of advanced semiconductor devices to detect electrical failures in-line. In the development stage, EBI can shorten process development cycle time and accelerate yield learning. In production, EBI has become a widely accepted addition to overall defect detection and yield enhancement strategies. Besides its ability to capture electrical defects in-line, e-beam inspection has proven more sensitive to certain critical ‘physical’ defects of interest (DOI) than optical inspection systems, because e-beam inspection utilizes a different contrast mechanism from that used for optical inspection. As a result, EBI is increasingly used to fill in some of the inspection gaps in the manufacture of advanced devices.

For this article, an e-beam inspection tool (eS31) was used to detect an electrical short between the gate and contact through the channel of the device. This defect was formed as a result of gate oxide loss, and was difficult to detect directly. After the contact was filled, it manifested itself as a voltage contrast defect that could be detected readily with an e-beam inspection system. This inspection can be performed after poly plug or after WCMP.

EBI Methodology
In the ramp stage of a DRAM device at SMIC Beijing, a certain number of wafers suffered a flip bitline failure. This type of bitline function failure resulted in a 6% yield loss. The blue die in the yield map in Figure 1 represents the flip bitline failure. The edge of the wafer was worse than the centre. SEM images of the defects after de-layering showed that the root cause was a cell contact short to the gate through the channel (Figure 2).

Figure 3 shows the schematic of the stack structure. Of the two cell contacts in the active area, one links to a capacitor and the other links to a bitline contact. The cell contact is a poly plug. Without annealing, the conductivity of the poly plug is low. The bitline contact is filled with a tungsten (W) plug. Because EBI has proven to be much more effective for inspection of the W plug, we decided to directly inspect the bitline contact layer by e-beam.

To detect the defect at the bitline W CMP layer, the beam conditions needed to be optimized. High beam current (125nA), low landing energy (500eV), and high extracting field (1500eV) were used to get a strong defect signal. A relatively large pixel (150nm) was used to obtain high throughput.

An example of the inspection results is shown in Figure 4. The defect map correlates well to the yield map shown in Fig. 1. Figure 5 shows a strong, bright VC defect: a W contact connected to the NFET, indicating a short. TEM results confirmed the root cause of this defect to be a cell contact shorted to the gate through the channel of the device, as shown in Figure 6.

Under low landing energy and high extracting voltage (1500V), the surface is positively charged, reverse-biasing the PN junction of the device. As a result, a smaller number of electrons are emitted from the surface.

Because the detector then collects fewer electrons, the normal W contacts appear darker. However, when a contact shorts to the channel, the PN junction is disabled and the detector collects more electrons from the substrate through the W contact. In our case, this made the defective contact appear much brighter than the normal W contacts, and it was detected as a bright VC defect.

The inspection results verified that the flip bitline function failure was caused by a cell contact shorting to the gate through the channel of the device; EBI was able to detect this killer defect. Finding this yield-killing defect enabled us to overcome this issue quickly.

To identify the root cause and solve this issue, a design of experiments (DOE) was carried out in the 300mm production fabrication line at SMIC, Beijing. The goal of the experiments was to determine the optimum process condition to eliminate the electrical short issue. A group of 5 wafers was split, processed under 5 different process conditions, and inspected on the eS31. To decrease experimental cycle time, the inspection point was moved from bitline W CMP to cell contact (poly plug).

The wafers were annealed to increase conductivity of the poly plug in order to ensure sensitive detection of the defects. A pixel size of 0,1Ìm, high extracting field and high beam current were used to maximize the defect signal.

Inspection results of the 5 split wafers are shown in Figure 7.

We concluded from the results that split condition 4 was the best choice to eliminate the short issue that limits product yield.

After the optimum process window was identified, we performed an inspection of the bitline W CMP layer to monitor this issue in-line.

Conclusion
Detection of a short between the gate and contact through the channel of the device was not straightforward. It required detailed analyses of the formation mechanism of the defect and its electrical characteristics and impact. The defect was best detected after bitline W CMP, using an ebeam inspection system capable of low landing energy and high extracting field. To shorten cycle time, the device was also inspected after poly plug formation, using an anneal step to increase conductivity.

The study showed that EBI provided a viable method to help identify and resolve the root cause of product yield loss. The alternative would have been to wait until completion of the full process and yield test, which would significantly delay the solution cycle time.

The wide range of operating conditions and high throughput of the eS31 proved critical for fast turn-around and production monitoring.

Biography
Yan Li received his Master’s Degree of Science in Material Science and Engineering from Tianjin University in 2005. He is currently a yield enhancement engineer at SMIC Beijing.

Henry Chen received his Ph.D. Degree in Chemistry from Tsinghua University in 2001. He is currently the yield enhancement manager at SMIC Beijing.

Robbinson Liu received Master’s Degree in Material Science and Engineering from Nanyang Technological University, Singapore, in 2001. He is currently an Applications Engineer at KLA-Tencor China.

Frank Fan received his Ph.D. Degree in Mechanical Engineering and Material Science from the University of California at Berkeley in 1998. He is currently an Applications Development Manager for e-beam inspection products at KLA-Tencor Corporation, San Jose, California.