News Article
New high performance transistor technology for 45-nanometer generations
Renesas Technology Corp. has announced the development of an extremely high-performance transistor technology with low-cost fabrication capability for microprocessors and SoC (system-on-a-chip) devices of the 45-nm (nanometre) generation and beyond.
Renesas Technology Corp. has announced the development of an extremely high-performance transistor technology with low-cost fabrication capability for microprocessors and SoC (system-on-a-chip) devices of the 45-nm (nanometre) generation and beyond. The new technology improves the performance of CMIS1 transistors with a proprietary Renesas-developed hybrid structure — an advanced technology that the company previously announced in December 2006. Like the previous technology, the new semiconductor manufacturing technology has a p-type transistor with a titanium nitride (TiN) metal gate and an n-type transistor with a conventional polysilicon gate. However, the new p-type transistor uses a 2-layer gate structure instead of a single-layer gate for better control of the threshold voltage2. Also, the new hybrid structure applies strained-silicon manufacturing techniques to boost current drive capability. These innovations produce about a 20-percent performance improvement compared to the previous Renesas hybrid structure. Importantly, the new structure can be fabricated at low cost because it requires no major changes to the current-generation manufacturing process.An experimental chip containing transistors with a 40-nm gate length has been fabricated. Data from tests performed on this chip have confirmed top-level drive performance: 1,068 µA/µm for the n-type transistor and 555 µA/µm for the p-type transistor at a 1.2 V power supply voltage.An element of the newly developed technology is the strained-silicon technique already widely used in cutting-edge semiconductor devices. The technique can be used in the Renesas hybrid-structure because the fabrication process of the structure's CMIS transistors closely resembles the transistors of a conventional CMOS process. The strained-silicon technique improves the drive performance in two ways. It distorts a channel part, forming a path through which current flows. It also widens or narrows silicon lattice spacing, enabling electrons and holes to move more easily.
