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European and Malaysian CMOS process technology agreement aims to scale 65-nm
Silterra Malaysia and IMEC have announced that they have signed an agreement for a joint development project (JDP) to create a foundry-compatible 90-nm CMOS process technology with intention to further scale to 65-nm.
Silterra Malaysia and IMEC have announced that they have signed an agreement for a joint development project (JDP) to create a foundry-compatible 90-nm CMOS process technology with intention to further scale to 65-nm. A 110-nm derivative will also be developed in parallel. This collaborative project is an extension of the JDP conducted earlier for the 0.13-micron (130-nm) technology and which is already in production at Silterra. The technology will be ready for production in the second half of 2008 or earlier and will, among other things, utilize low-K inter-metal dielectric and the 193-nm patterning process. The smaller geometries will allow for smaller die sizes and faster transistors. A team of Silterra and IMEC engineers will fine-tune the base-IMEC process at IMEC's research facility in Leuven to meet the specifications defined by Silterra. The process will have physical design rules and electrical characteristics that match mainstream technologies, enabling customers to seamlessly support their multi-foundry sourcing strategy."More advanced process technology development is essential to support the success of our customers. Many of our major customers adopted the multi-foundry strategy and we will continue to grow with them. This project paves the way towards future technology nodes and a migration path to 300mm," said Kah-Yee Eg, CEO of Silterra. "As proven in our earlier engagement with IMEC, this JDP will enable Silterra to bring a new process into production quickly." "We are very pleased that we will continue the successful collaboration with Silterra to develop a foundry process that will benefit such a wide customer base," stated Prof. Gilbert Declerck, president and CEO of IMEC. "Our 90-nm platform technology is a great starting point to build on because it is proven and will help shorten development cycle times significantly."The new process, like Silterra's own foundry compatible 0.13- and 0.18-micron logic technologies, is targeted for a wide range of products for consumer, communications and computational applications. In addition, the technology is also optimized for CPU, DSP and graphics applications. This jointly developed foundry process opens the door for Silterra to collaborate with other foundry players in rapidly bringing advanced node densities to production. "We see significant business growth in the next 2-3 years and will continue to actively invest in process technology," said Eg. "We had built up strong in-house capabilities in developing process technologies for specific applications such as RF, High Voltage and Low Power in 0.18-micron for the past few years and we are currently developing these application specific process technologies on 0.13-micron. We will continue to move these technologies down to 90-nm and 65-nm with our customers."
