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An Automated Tool For Double-sided Overlay Metrology

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The use of backside patterning is experiencing strong growth due to the increasing popularity of MEMS devices, 3D Integration and communication products. The constant demand for new device features such as through-silicon vias (TSV’s) as well as greater functionality within existing devices has fuelled a demand for more efficient use of wafer real estate on the front and backside of the wafer. Keith A. Cooper and Thomas Huelsmann, SUSS MicroTec discuss.

The use of backside patterning is experiencing strong growth due to the increasing popularity of MEMS devices, 3D Integration and communication products. The constant demand for new device features such as through-silicon vias (TSV's) as well as greater functionality within existing devices has fuelled a demand for more efficient use of wafer real estate on the front and backside of the wafer. Keith A. Cooper and Thomas Huelsmann, SUSS MicroTec discuss.


Many modern-day device layouts are requiring frontside to backside overlay of 1µm; this trend toward smaller feature sizes and tighter front-back registration has driven a need for frontside to backside overlay metrology tools. And as backside patterning moves toward greater production volumes, so also must the backside metrology tools provide automated measurement for production scenarios.


The concept of double-sided patterning is not new - it has been present in the process flow of MEMS and communication devices for many years. Si pressure sensors, GaAs telecom chips, InP lasers, and many other such devices have utilised the backside of the wafer, either for device functionality or due to cost pressures to capture and utilise otherwise wasted substrate real estate.


The earlier uses of backside lithography employed viewing systems with infrared (IR) illumination; the proper choice of IR illumination source coupled with an IR-sensitive camera yielded sufficient clarity in the image to perform alignments of frontside to backside features on many materials including GaAs, InP and in some cases Si. But not all substrates yielded a reasonable image to align, particularly metallized circuits, Si substrates with high B-doping levels, or other inherently IR-opaque materials such as Al203. Due to this material opacity problem and the need to perform tighter front-back alignments for smaller features, savvy equipment suppliers designed imaging systems which employ imagecapturing software so that back and front of substrate can be viewed with even highly opaque materials. Despite the ease of use and therefore popularity of this double-sided alignment technique, IR is still valuable for buried circuit layers and other device layouts or process schemes.


Decreasing Device Dimensions
Many of these devices have undergone the typical shrinkage of geometries in order to make the circuits smaller, faster or more cost-competitive. With this reduction in feature size comes the requisite tightening of alignment tolerance for front-front or front-back overlay. This progression is only natural as the devices become more mature or as the cost of such circuits is reduced in an effort to create broader market appeal. In their 2006 Global MEMS newsletter, Yole Developpement has projected a 13% CAGR across many MEMS devices alone, with many of these requiring backside patterning and the corresponding metrology steps.


But as the market for such devices matures and the production volumes ramp significantly, so does the need to automate the process steps to keep the cost of ownership (COO) in line with market demand.


There is a clear and present need for automated metrology systems to provide process control for processes requiring backside alignment. The requirements of such a tool would include:


● Hands-off metrology on various sized wafers up to 8.”
● Robotic handling to process various sized, often fragile, substrates with high throughput
● Access to multiple arbitrary measurement locations for process and metrology flexibility
● Repeatability, reproducibility, and accuracy
● Diagnostics/ Factory Automation: autocalibrate, auto-diagnostics, SECS/GEM



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Figure 1 shows a block diagram in plan view of a tool designed to meet these requirements. With a granite base for machine stability and a flat reference surface, the tool incorporates an XY translation stage mounted atop the granite so that all motions are carried out with minimal friction. This granite has been polished to a total surface finish of 2µm over its entire surface to minimise or eliminate the need for re-focusing between measurement sites.


Automated Processing
A field-proven robotic handling system with a noncontact prealigner (Figure 2) also provides a fast and easy method to change wafer sizes or materials without any mechanical changeover of prealigner or robot end-effector. Since the tool operates completely in a hands-off mode, it can measure and report frontside to backside metrology results at a throughput of 50 wafers/hour, and the results are completely independent of the operator. Edge handling is also available for those applications where exclusion areas on the wafer dictate a certain rim of handling area. This feature is especially attractive for optolelectronic or MEMS applications where the optical and mechanical functionality of the features is particularly susceptible to damage from handling.



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To provide freedom and flexibility in choosing the overlay verification sites, the chuck has large viewing areas with unobstructed access to the top and bottom sides of the wafer. (See Figure 3) This ensures not only that features critical to the device's performance will be visible, but also that there is no optical shift and ensuing overlay offset in the measurement process created by any uncharacterized optical aberrations in the chuck material. More than 4000mm2 on a 6” SEMI wafer is available for viewing.



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The measurement of the top-bottom overlay is carried out by a vertical superimposed microscope, depicted in Figure 4. The measurement technique is to simultaneously view the top and bottom fiducial images with CCD cameras, then determine the relative position of these two targets using a pattern recognition algorithm based on the Cognex Patmax software. Typical fiducials for the overlay metrology tool are the same as those used for preceding lithographic alignment; targets may be between 30 and 300µm, and are most typically about 100µm in X and Y. The Cognex system utilises a very durable and field-proven software platform so that the system is impervious to variations in contrast, rotation of the images, and even reversal of the image tone.


After determining top-bottom overlay at this first site, the alignment stage is automatically moved to position the alignment fiducials for each of the desired locations into the field of view of the cameras and the process repeats.



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Precision Problems
One main challenge in precisely measuring the alignment accuracy of structures on the top and bottom side of the wafer lies in several mechanical imperfections that occur during operation, like the offset between the optical axis of the microscope. In order to maintain control of these deviations each time a wafer is measured, the DSM200 rotates the substrate automatically by 180° at the end of the first measurement cycle, as depicted in Figure 5. In this way errors such as misalignment in the optical axis of the microscopes can be eliminated so the final result is accurate and trustworthy for all measurement sites.



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The final overlay between the top and bottom target is calculated by the following:



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For any metrology tool to be effective, it must deliver consistent results as measured by repeatability and accuracy. To measure repeatability, a Si wafer was printed on a doublesided lithography tool from SUSS MicroTec, followed by development of the resist features to create optically visible lithographic features. After development of the resist, the patterned wafer was loaded into cassettes and measured in the DSM200 tool as described above.


Detection repeatability can be quantified by loading a sample into the measurement tool, recording the indicated overlay repeatedly, then performing statistical analysis of the output data. Detection repeatability can be explored further by unloading and loading the same sample multiple iterations, measuring the overlay each time and analysing the data for evidence of drift or fluctuation.


Potential sources for detection repeatability error would include mechanical drift in the stages for wafer chucking or objective/camera mounts, uncertainties in the position detection algorithm, vibration in the tool, and thermal drift. Any one of these sources can contribute significant error which would dis-qualify the tool for its intended use, and must be carefully considered from a system-level point of view from the ground up when designing the tool.


Measurement accuracy for the tool was quantified by means of measuring a transparent substrate with very thin patterns of Cr on one side, similar to a lithographic photomask. A quartz substrate, 1mm thick, with optical transparency and consistency parallel to photomasks was patterned with a laser writer, then the patterned features were transferred into the underlying Cr layer by means of dry etching. The overlay of these Cr images can be measured by a benchmark topside-topside metrology tool such as the Vistec LMS. Then this wafer was measured on the SUSS DSM200 by using the top side microscope to look at one top side feature while the bottom side microscope looks also at the same feature (for an anticipated 0µm overlay) or an adjacent top side feature (for an anticipated 20µm overlay), as shown in Figure 6.



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Strict Control in Margin of Error
For any metrology to meet the measurement requirements, it needs to deliver a very tight grouping of overlay readings, indicating a very high detection repeatability. Results from the tests described above for the DSM200 are depicted in



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Figure 7, with 2000 total measurement cycles at multiple sites. The data indicate 0.035µm for the X direction and 0.067µm for the Y direction, both at 3 sigma, indicating that the tool does supply the requisite detection repeatability for a frontback overlay requirement of 1µm or better.


Even if a metrology tool can repeatedly detect the apparent overlay error between 2 features, this information is nearly useless unless there is likewise a correlation between the metrology tool's results and some external measurement standard. Results from the accuracy tests using the transparent substrate with Cr features are plotted in Figure 8 and show a mean + 3 sigma value less than or equal to 0.15µm, well within the range of performance required for current or coming generations of devices requiring front-to-backside overlay.



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Conclusions
A growing demand for high quality frontside to backside lithography processes has likewise generated a need for an accurate, automated tool to quantify the overlay for such processes. Operating in a cassette-cassette mode for high throughput, such a tool has been designed and qualified to provide overlay metrology for technologies such as 3D Integration, MEMS and other devices with front to back registration requirements down to 1µm or tighter.



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