Info
Info
News Article

Laser-Based Dicing: Doing Thin Better

News
Almost every silicon wafer is eventually “diced” into single chips. For unthinned wafers, laser dicing still lacks the required throughput and cost-effectiveness favours less accurate blade-saw singulation techniques. Wafers are being increasingly thinned to meet demands for more compact electronic consumer products. Here Delphine Perrottet, Billy Diggin and Brian Farrell of XSiL review the prospects of the technology.

Almost every silicon wafer is eventually “diced” into single chips. For unthinned wafers, laser dicing still lacks the required throughput and cost-effectiveness favours less accurate blade-saw singulation techniques. Wafers are being increasingly thinned to meet demands for more compact electronic consumer products. Here Delphine Perrottet, Billy Diggin and Brian Farrell of XSiL review the prospects of the technology.


As a fundamental building block for devices in electronic goods, silicon wafers are particularly important to the semiconductor industry. The worldwide silicon wafer area shipments increased by 20% in 2006 over 2005 shipments. According to the SEMI Silicon Manufacturers Group, this equated to 7,996 million square inches. They also note the significant demand increase for 200mm and 300mm wafers, particularly for memory products. Since practically every silicon wafer that is produced must be singulated data, this represents important evidence of new capacity requirements for 300mm wafer dicing and possible expansion of existing capacity for 200mm wafer dicing. As a macro view of the dicing landscape, it paints quite a positive outlook.



""



Laser dicing technology is presently not competitive for standard thickness wafer dicing, primarily for reasons of inadequate throughput when compared to blade sawing. However, two specific trends are changing this. Firstly, wafer thinning to below 100um is increasingly being utilised in high volume applications. There are expectations in the industry that 30% to 50% of silicon wafers will be thinned by the end of the decade. Secondly, the industry and leading companies therein indications are that this will continue. Several leading manufacturers have roadmaps to reduce from 75um down to 25um and even thinner. One of the leading sectors of thin wafer adoption is flash and multi-chip packaged memories, where multiple die are stacked in a low profile package. The primary drivers for this production include but are not limited to mobile computing, mobile media and wireless communications. This results in not only lower overall packaging costs, but also greater performance and increased storage, in the same or smaller footprints. While creating new process issues for existing dicing methods, these trends in the dicing landscape have opened new doors of opportunity. It is with thin silicon wafers that laserbased dicing now has a competitive advantage.


Industry Issues for Thin Wafer Dicing
Yield from the overall packaging process is vital, but more so in recent times. As packaged devices become more complex, there are more involved and evermore interrelated process steps; backgrinding to thin wafers to ever decreasing levels, stress relieving steps, mounting onto die-attach films (DAF), thin wafer and DAF dicing, new wirebonding techniques for multi-level chips, etc. The challenge for all packaging manufacturers is attaining and sustaining high yield. One can imagine a mini-SD 4GB Flash device with multiple die in a stacked configuration; the opportunities for failure and the cost of yield loss on the entire packaged device is now far greater than that on a single
die package. It is well recognised in the industry that die strength of thin die is an important factor in package yield. Present techniques for singulating thin silicon wafers are facing increasing difficulties. The predominant mechanical saw dicing method is encountering cost-of-ownership issues. Yield is the largest factor, but so also is reduced throughput and rising consumable costs.



""



Traditionally, the ratio of the bulk silicon layer to the patterned device layer has been large enough to not present undue blade dicing concerns. Now with thin wafers, this has changed significantly. It is not uncommon to have for example a 6-10um patterned layer, 75um of silicon and 25um of die-attach film. In this scenario, under the mechanical impact of saw blades, the wafer is less able to withstand stresses induced in the process. This can result not only in increased chipping, cracking and delamination, but also poor DAF singulation causes greater stresses on the wafer. Resulting not only in increased chipping, cracking and delamination, but also poor DAF singulation and lower die strength - ultimately lower yield.


To somewhat overcome this, more expensive dual spindle saws are required so that one blade type makes a step cut and other makes a through cut. Needless to say, there are increased consumable costs - more frequent blade changes, more DI water consumption. In addition, it is reported that dicing speeds have to be reduced significantly, to about 25-30mm/s. This increase in capital cost and consumable costs with a reduction in throughput is a hard pill to swallow. To make matters worse, as wafers get ever thinner, these yield and throughput issues become more onerous. Because of increasing cost pressures, chip manufacturers are actively seeking alternate solutions to achieve higher yield with higher throughput - a better cost-of-ownership (CoO).


Laser-Based Dicing
One solution to a better CoO comes from XSiL, who are launching at Semicon West in 2007 a new laser-based product specifically designed to address the issues associated with thin wafer dicing. Branded as the X300D+, the product's primary strengths are high throughput and better yield (with particular emphasis on die strength). When coupled with low consumable costs, it provides a competitive CoO. And as wafers get ever thinner, the CoO gets ever better. More about that later!



""



Neither blade nor laser alone is sufficient to achieve and maintain higher yields on thin wafer dicing. While the laser approach achieves high throughput and can contribute to higher yield, an additional process is required to complement laser dicing to address die strength. In the X300D+, a laser-based approach is complemented by an innovative process called MaxFlex to provide die strength enhancement after dicing. In addition to this process, the system includes coating and cleaning activities.


The first process step is coating, where a non-ionic, watersoluble coating is dispensed onto the wafer and spin-coated for uniform coverage. This provides a low-cost, high-performance protection to the wafer to prevent and reduce risk of wafer contamination. The coating's main function is protection — ensuring yield is maintained. This coating was selected after rigorous process development and trials. Due to its water-soluble nature, it does not require complex removal or treatment methods as may be the case with other, different coating formulations.


The second process step uses a high-powered UV DPSS laser to machine the thin wafer. The proprietary processes and techniques used in this step provide the ability to machine silicon and DAF with low damage and no chipping — ensuring high yield. Using a combination of laser and scanning galvanometers, this dicing process reaches high speed. This speed scales upwards as wafers get thinner. For example, for a 75um silicon wafer with 20um of DAF, speeds of up to 100mm/s can be achieved whereas for 50um of silicon and 20um DAF, this can scale to more than 230mm/s. No DI water is used in the dicing process and laser diode lifetime before replacement is of the order of years.


The third process step is wafer wash. Here, the coating and debris are removed, providing a clean diced wafer. The level of DI water consumption is minimised to less than 1 litre per wafer. The final process step is an innovative low-cost dry-etch process called MaxFlex. It has been developed and designed for thin diced wafers and its sole purpose is to increase overall device yield. It performs a stress-relieving function on the silicon sidewall of each and every singulated die on the wafer. This is analogous to dry polishing or CMP after backgrinding processes. The MaxFlex process performs its stress-relieving task by etching or removing, in a highly-selective fashion, up to 5um of silicon from each and every die sidewall. The net result is die strength enhancement — directly improving device and package yield. Etch costs vary not only with the amount of exposed silicon but also directly with the depth of etch. Users can elect to etch only the requisite amount of silicon for the desired level of die strength enhancement.


While this laser-based approach provides high throughput and high yield in comparison to other offerings for thin silicon dicing, it also provides low consumable cost in exchange for this level of yield. With low coating costs, minimal DI water consumption and directly attributable etch to yield costs per wafer a more competitive CoO is attained. As wafers get thinner, there is more good news for device and packaging manufacturers. Laser dicing speed increases resulting in increased throughput for the same high levels of yield. In addition, consumable costs decrease as the etch cost reduces in proportion to the area of exposed silicon after dicing. This results in an ever improving return on capital and removes some of the technical and cost barriers to widespread thin and ultra-thin wafer adoption.



""



Results
As shown in Figure 1, the MaxFlex process significantly improves die strength. The mean die strength is increased by a factor of 5 compared to basic laser dicing, and more than 1.5 times greater than the corresponding DBG value (dicing before grinding with an abrasive saw). Figure 2 shows the edge of a silicon chip diced with a UV laser. The thickness of 75 µm was through-cut at 50 mm/s to ensure the best sidewall quality. Figure 3 shows the edge of a 75 µm silicon chip on DAF after dicing. Both SEM images were taken after MaxFlex has been applied. Figure 4 shows a diced patterned wafer front side before and after cleaning.


Conclusions
For thin devices and stacked packages, yield is more important to chip manufacturers than never before. Manufacturers care about CoO but this is under significant pressure for thin wafer dicing because of lower yield, lower throughput and rising consumable costs. As wafers are getting thinner, these issues are harder to overcome. A laser-based approach with associated processes for yield provision offers an alternative. Higher throughput dicing coupled with higher yield, particularly through die strength enhancement, is now becoming available to manufacturers. In combination with low consumable costs and with thinning industry roadmaps, laser-based dicing is positioned to provide not only the best CoO for thin wafer dicing, but also an increasing return on capital expenditure well into the future.



AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS
Can New Advances In CMOS Replace SCMOS Sensors In Biomedical Applications?
SUSS MicroTec Opens New Production Facility In Taiwan
TEL Introduces Episode UL As The Next Generation Etch Platform
U.S. Department Of Defense Partners With GLOBALFOUNDRIES To Manufacture Secure Chips At Fab 8
GOODFELLOW Confirms Membership In The BSI UK Graphene Group
Cadence Announces $5M Endowment To Advance Research
Changes In The Management Board Of 3D-Micromac AG
Onto Innovation Announces New Inspection Platform
ASML Reports €14.0 Billion Net Sales
EV Group Establishes State-of-the-art Customer Training Facility
New Plant To Manufacture Graphene Electronics
Siemens And ASE Enable Next-generation High Density Advanced Package Designs
South Korean Point Engineering Chooses ClassOne’s Solstice S8 For Advanced Semiconductor Plating
ITRI And DuPont Inaugurate Semiconductor Materials Lab
Tower Semiconductor Announced Program Creating An Integrated-Laser-on-Silicon Photonics Foundry Process
K-Space Offers A New Accessory For Their In Situ Metrology Tools
DISCO's Completion Of New Building At Nagano Works Chino Plant
Tescan And 3D-Micromac Collaborate To Increase The Efficiency Of Failure Analysis Workflows
Panasonic Microelectronics Web Seminar
Imec Demonstrates 20nm Pitch Line/Space Resist Imaging With High-NA EUV Interference Lithography
Belgian Initiative For AI Lung Scan Analysis In Fight Against COVID-19 Goes European
Obducat Receives Order For Fully Automated Resist Processing Tool From A Customer In Asia
AP&S Expands Management At Beginning Of 2021
Will Future Soldiers Be Made Of Semiconductor?

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification} Array
Live Event