New technology developments require, advanced methods of manufacturing. Dr Yiping Song and Dave Thomas, Aviza Technology discuss the versatility of using Si etch and polymer deposition to improve results using the Bosh Process.
Introduction to Deep Silicon Etching using the Bosch Process
The MEMS market is not only growing but is evolving at a tremendous pace. Technology developed for MEMS device fabrication has been gradually adopted in other areas of the semiconductor industry. Deep Si etching is capable of delivering process attributes with a high degree of control and within a common process module design. Dr. Yiping Song and Dr. Dave Thomas Aviza Technology, Inc. describe switching between Si etch and polymer deposition to achieve high selectivity and high rate requirements using the Bosch process.
Deep silicon (Si) etching using the Bosch process was initially developed to cater to the needs of the MEMS market. Driven by consumer applications such as MEMS microphones in cell phones, accelerometers in consumer gaming applications, and automotive pressure sensors, the MEMS market is growing at a tremendous rate. According to Yole Développement the total MEMS device market in 2005 was valued at ~$5.3B and the total MEMS equipment market is set to grow from $631M in 2005 to $861M by 2010. Deep Si etching is a key enabling technology in the manufacturing process for MEMS.
Recently, however, deep Si etch technology has also been adopted in other areas of semiconductor manufacturing, particularly for wafer-level packaging (WLP) and new designs of high voltage power devices. One example of a MEMS application is a pressure sensor - one of the fastest growing applications in industrial automation. For this application, typically a large well is etched through the Si substrate from the back-side to leave a membrane at the front-side for pressure sensing. Figure1 shows an example of a silicon well. For power devices it is common to etch a deep trench for high voltage isolation that is subsequently filled with dielectric or a combination of dielectric and polysilicon. One form of (WLP) is 3 dimensional chip stacking where two or more dies are stacked to form small form factor, high performance packages. Metal filled vias formed by deep Silicon etch processes form the die to die connections; usually called Through Silicon Via technology, (TSV). A broad range of IDMs, foundries and packaging houses now have active 3D stacking programmes. It is becoming apparent that the Si via etch cannot be treated in isolation because the characteristics of any particular process will affect the next process in line. Only by understanding the integration of Si via etching, oxide deposition, and PVD seed layer metallisation can successful TSV's be realised. Figure 1 shows an example of a TSV.
The two examples differ tremendously in terms of depth, critical dimension (CD), profile, and aspect ratios. Deep Si etching is moving from an R&D phase into mass production as MEMS production capacities ramp and as it becomes an essential building block for mainstream applications. As a result, emphasis is increasingly placed on the production-worthiness and overall repeatability/reliability of deep Si etch equipment, together with high throughput, high uptime, and low cost of ownership. To meet these requirements, production proven engineering techniques are required that ensure the highest equipment reliability & optimum process repeatability. One of the important aspects for achieving high productivity is the capability of using wafer-less plasma cleans in order to maintain stable chamber conditions.
Bosch Hardware Description
Essential components for the Bosch process include gases which can be switched on and off typically at cycle rates between 1 & 3 seconds. One of the gas lines is used to feed etchant gas, e.g. SF6, while another one to feed deposition gas, e.g. C4F8, into an etch chamber alternately. These gases pass through a plasma generation region, whereby SF6 is dissociated to produce reactive Fatoms for high rate etching and C4F8 is dissociated into polymer forming precursors such as CF2 for deposition. In the process chamber, a wafer is clamped to a platen, ideally using an electrostatic chuck.
The platen serves two purposes: (1) it is powered by an RF generator to control ion energies for process control, and (2) it is fluidcooled to remove heat generated by the wafer surface reactions. A high capacity turbo pump is also needed to maintain the process pressure and high gas flows.
Bosch Process Description
The principles of the Bosch process can be illustrated by the pictured diagram. Step by step descriptions are as follows: (Figure 2).
a. The initial step is an isotropic etch into the Si substrate masked either by oxide or photoresist. Fluorine dissociated by the plasma source can react with silicon spontaneously and exothermically. This is how high etching rates can be obtained. Due to the very low bias power, the mask etch rate is extremely low, to obtain very high selectivities. The chemical nature of this step leads to isotropic etching.
b. After the initial isotropic etch, a polymer deposition step conformally covers all surfaces of the wafer.
c. Next, an anisotropic polymer etch step opens the bottom of the feature to reveal the Si surface. At the same time, polymer on the top surface is removed. However the main purpose of this step is to clear polymer on the Si surface while leaving polymer coating on the sidewall.
d. The process is looped back to step “a” for another isotropic etch. In the diagram “d”, the thickness of polymer on the sidewall is thinner than that after step “c”. This is because of some lateral polymer erosion in the isotropic etch.
e. After a number of loops (14 shown in the diagram), a net anisotropic feature is created.
Due to the switched nature of the Bosch process, ripples on the sidewall (usually called ‘scallops'), are present on a microscopic scale. Therefore the process is usually used for cases where such scallops do not compromise device performance.
Flexibility of the Bosch Process
For practical applications, the process is tailored for specific applications.
For through-wafer-well etching to create thin membranes for sensor applications, highest selectivity to the membrane is required. A selectivity limitation is the anisotropic polymer removal step which often requires modest platen (bias) power. In order to optimise selectivity, it is desirable to have a thick polymer deposition on the sidewall to enable a long isotropic step to follow. This may result in large scallops but this is a reasonable trade-off for this type of application.
In MEMS applications that do not require high selectivity to underlayers or a high accuracy of profile control, having a high etch rate is typically the most important parameter. To achieve this, high pressure, high gas flow, and high source power are needed to generate sufficient reactive species to react with the Si. In this regime the exposed (etching) area also becomes a factor due to micro-loading.
Power MOS applications often require high aspect ratio trenches etched into Si and stopping on a buried oxide layer (BOX). The trenches created often need to have a straight and slightly tapered sidewall with relatively smooth morphology. Also required is a minimal notch at the interface between the Si and the BOX. These are requirements for subsequent thermal oxidation and poly-Si filling and to enhance overall device performance. In such cases small scallops are needed to ensure sidewall smoothness. Hence a low operating pressure becomes important. Good polymer passivation is still needed due to the high aspect ratios involved so a relatively higher degree of anisotropy during the polymer removal step is helpful. Bias modulation is also used for notch prevention that would otherwise be caused by charge build-up at the Si/BOX interface.
In 3D packaging, high etch rate is a requirement for TSV, including high resist selectivity, and sometimes high aspect ratio capability. To achieve these requirements at the same time, moderately high pressure is needed for the etch rate but a multi-block approach is common to reach the high aspect ratio.
Deep Si etch processes are being increasingly adopted for the growing MEMS market but also within more mainstream applications such as power and 3D packaging. Its role as a flexible enabler for new product ranges and methodologies will continue to expand and proliferate. The next 1-2 years will see the implementation of deep Si etching on 300 mm wafers particularly for 3D packaging activities.