Lithography

The potential of double patterning immersion lithography for the 32nm half pitch node

To extend the capabilities of current 193nm water immersion lithography towards the 32nm node, double patterning lithography is a promising option as it pushes the k1 factor below its theoretical limit of 0.25. Vincent Wiaux, Greet Storms, Shaunee Cheng and Mireille Maenhoudt, IMEC, Belgium discuss how, by breaking down the different contributions to CD uniformity (CDU) and overlay, the needs for improvement can be identified to meet requirements of the 32nm node, taking a baseline LELE process as example.

Today, strongly driven by the needs to develop 32nm node and beyond processes for memory applications, scaling is continuing at a very aggressive pace. This calls for a lithographic patterning capability that is beyond the resolution of ArF water-based immersion tools. Even when approaching the practical limit of 1.35NA it requires patterning features at an effective k1 below 0.25, which is the theoretical limit for single-exposure lithography. Alternatively, high-refractive index materials (enabling a higher NA) and EUV tools are currently under development, but it is questionably whether they will timely become available for production. Therefore, double patterning immersion lithography is currently being investigated as an intermediate solution to meet the resolution requirements of the 32nm node. In double patterning, instead of printing e.g. a 32nm line and a 32nm space at one time, the pattern is split to pattern twice a 32nm line at double pitch (i.e. 128nm pitch) to get at the end 32nm features at 64nm pitch through a double patterning process flow. Contrary to double exposure, the two images do not interact in the resist layer when using double patterning. This effectively reduces the k1 factor to below 0.25.

Design Split
Double patterning lithography implies splitting the design on two separate designs, together with implementing a double patterning integration flow. This technique shows the potential of extending lithography beyond the classical resolution capability, but raises new challenges related to mask design and mask manufacturability, integration flows, critical dimension uniformity (CDU, a measurement of how uniform the critical dimensions are from structure to structure) and overlay (referring to the positioning of one mask layer over the other). In this article the basic double patterning process flows and the steps towards an automated design split of twodimensional patterns are discussed and demonstrated. Next, process and metrology challenges related to CD and overlay control are taken into consideration. Finally, experiments demonstrate the potential for improving CDU and overlay to meet the 32nm requirements.

Litho-Etch-Litho-Etch Approach
Two basic process flows can achieve pitch doubling through double patterning: the dual line approach and the dual trench approach (figure 1). In principle both approaches can be used to pattern either a trench dark field (DF) layer or a line light field (LF) layer.

While those processes are clearly defined, the associated patterning steps have multiple implementation options, presenting a range of different requirements, capability and limitations to meet resolution and control budgets, also depending on the application. If the double patterning technique will be accepted in a full manufacturing flow, it will require implementation of both process options in order to address pitch doubling on front-end and back-end layers.

Demonstrations of both types of processing have been accomplished on dry and immersion scanners. Figure 2 shows 32nm half pitch (top) and 45nm half pitch (bottom) structures (32nm node Flash and logic design rules respectively) patterned into a 100nm thick poly layer using an oxide hard mask in a dual line patterning process. The hard mask is still visible on top of the structures that were patterned in the first step (images on the left). For these experiments, 193nm lithography with NA=1.2 (water immersion, ASML XT:1700Fi) and annular illumination settings were used.

Currently, more cost-effective process flows are being investigated. For the dual line process, for example, a possible improvement consists in skipping the intermediate etch step by treating the first litho pattern such that the second resist layer can be coated and patterned on top of it.

Split of Two-Dimensional Patterns
The design split of two-dimensional patterns into two separate layers is an important key for the success of double patterning. Dependent on the pattern density, including 2D content, and dependent on the application of the features that need to be patterned (contact holes, logic metal or poly, Flash-like structures…), different split strategies are possible, each having specific challenges and limitations.

Split and optical proximity correction (OPC) of a 32nm half-pitch poly design is shown in figure 3. This split is an intuitive feature-based split, where the dense lines have been placed alternating on mask A and mask B, thus doubling the pitch. After patterning using the double line process, the final image after poly etch is shown.

At the 32nm node, random logic applications need less aggressive pitches, namely 45nm half pitch; but it presents higher 2D content and thus more challenges for the split. Split and OPC of a 45nm half pitch logic cell is shown in figure 4. The split in this case had to eliminate sub-resolution pitches and small spaces, requiring the cutting of polygons. This leads to the need of ensuring robust stitching through process variations. Patterning is done using the double-line process; top-down SEM images are shown for each patterning step. Also the final image after poly etch is shown.

When the double patterning technique is to be used in a production environment, full chip designs need to be split in an automated way. This requires setting up design split rules that lead to an optimum cutting and stitching strategy, where a trade-off needs to be found between scripting complexity and design regularity.

For some applications, split conflicts arise which can only be solved by applying design restrictions. IMEC is currently running a systematic investigation of the constraints to ensure designs to be split-compliant. Work is also done in collaboration with main EDA vendors that develop the software.

CDU and Overlay
In a commonly used double-patterning process, i.e., the double-line LELE process, lines are printed and etched into a hard mask. This is followed by printing and etching a second series of lines onto a second hard mask or substrate. The final image is a combination of two sets of lines and hence, of two CD populations since there are differences in wafer stack, wafer topography and etch characteristics between the two steps. For such a process, tight overlay performance becomes critical in order to avoid misalignment of the two alternating groups of lines.

The process challenges related to the existence of two CD populations bring along new challenges. Specifications are tighter, and the metrology errors will begin to contribute to the final budget. The different populations will have to be distinguished in tests and measurements. This will allow the application of process adjustments to match the CD means and CD control of the two populations. Secondly, it will be necessary to measure the overlay inside the double patterning structure.

CDU Challenges
A thorough CDU characterisation requires the development of an accurate CDU model that is capable of ranking the error sources to CDU and of predicting the requirement for manufacturable budgets.

A first experiment to measure CDU for a 32nm HP double patterning process consisted in exposing wafers on a 1.2NA immersion scanner without optimisations like etch adjustment or dose corrections. After exposure, etch, strip and clean, a second exposure was performed. After each processing step, every wafer was measured to determine a full wafer CDU spatial and statistical distribution. The etch bias is determined by plotting the difference in mean CD after litho and after etch. The total CD control will include the ability to maintain the final CD on target and thus to control the CDs and CD biases at every litho/etch transfer mask (Fig. 5)

Simulations show that a more uniform wafer CD distribution could be obtained by minimising the mean difference between the CD populations, by compensating for intrafield CD variation and by optimising the etch variation across the wafer. These modelled results demonstrate the potential capability to achieve sub-3nm CDU, which is the requirement for 32nm halve pitch CD control, assuming all corrections of systematics can be applied.

Shown in figure 5a is CD mean (left chart) from litho to final poly for CD1 and CD2 respectively. CD1 and CD2 are line width in poly resulting from litho1 and litho2 respectively. Different etch bias for CD1 and CD2 demands precise litho1, litho2 targeting and CD control at every litho and etch step. 3σ CDU (right chart) shows progression of CD control after each DP step without any correction for the systematic errors.

Overlay Challenges
A very similar approach was used to enable an optimisation of the total overlay control. This demands minimising mask registration error between the split layers as well as being able to model and to compensate for tool and process induced systematic layer-to-layer fingerprint. For the experimental part, the in-die, at resolution double patterning overlay data have been measured. In practice, the overlay is obtained from 32nm HP structures by measuring two adjacent pitches using scanning electron microscopy (SEM) and comparing their mean to the designed pitch. Overlay analysis is modelled and analysed using MonoLith.

An adequate dense sampling was implemented to allow modelling of wafer overlay distributions. Modelled correctable components showed consistent wafer to wafer results. After correcting for interfield (wafer) distributions, the simulated residual fingerprint indicates that an overlay of better than 4nm could be achieved.

Conclusion
The feasibility of using double patterning lithography for the 32nm node has been investigated on a 1.2NA lithography system. Very promising double patterning results were obtained by splitting gate levels of 32nm half pitch Flash cells as well as logic cells in two complementary designs. Cost-effective process flows, automated mask design splitting, CD and overlay control, and metrology have been recognised as the critical challenges to meet manufacturing requirements and make it a reproducible process.

Process requirement of a 32nm half pitch double patterning process demands CD and overlay control below a 10% level, i.e., below 3 to 4nm. However, the presence of two CD populations in the final image gives rise to more aggressive individual specifications and to new metrology challenges. Via experiment and modelling, the potential of improving CDU to 2.5nm was demonstrated. Similar work has been done for modelling overlay. The results indicate that an overlay of better than 4nm can potentially be achieved.

Although the simulations still have to be validated in further experiments, with these results it seems feasible that the 32nm resolution can be manufactured using this approach.

The authors would like to thank the DP team at IMEC, the ASML DP team and 1700i support, Synopsys and Mentor Graphics for initial split of the test clips, and Hitachi for metrology support.