Chip Manufacturing

Scaling prospects for RF CMOS

Radio frequency transmissions need different sorts of electronic technologies from those used in pure digital devices. As CMOS transistor technology advances can it take on these more extensive challenges? Dr Mike Cooke investigates.

In the 120 years since Heinrich Hertz laboratory experiments producing and detecting electromagnetic waves (1887), the use of wireless communications has changed the life of people on Planet Earth beyond recognition. Until recently, mass consumer contact with Hertzian waves (also known as radio) has been first through audio and then television reception, while in the background radio has been used for civil and military communications, radar, etc.

The main reasons why mass contact was restricted to reception technologies were the much higher powers needed to transmit radio waves over any appreciable distance and the need to restrict access to a finite number of radio channels. The power requirement for transmission, in particular, limits the ability of mobile units to operate. As proposed in the 1940s by Bell Labs researchers, the cell phone concept overcomes these two problems by only requiring the mobile unit to transmit over a short distance to a reception/transmission tower at its local base station connected to a wire line network (Figure 1). This reduces both the needed transmission power and the cluttering up of radio channels since another mobile phone at sufficient distance can use the same radio channel for its transmission to its nearest base station tower.

The penetration into a true mass market, ranging from the “developed” to “developing” world, has only taken place in the last ten years or so. This required both the development of technology and of a higher density of cells so transmission could be made over shorter distances, reducing the power requirements for handsets. Previously, cell phones had existed as bulky luxury items, first as units in automobiles and suitcases, and later in the famous brick-sized format of the 1970 and 1980s; now, mass consumers have access to devices just a few cm in size. From tens of kilograms, modern handsets typically weigh in at less than 100g. The rise of the mobile phone constituted something of a lifeline for the semiconductor industry at a time, the late 1990s, when the early explosive growth of the personal computer market was subsiding and the collapse of the internet bubble was on the horizon.

Although the mobile phone has stimulated development of a number of technology areas, such as non-volatile memory (Flash) and digital audio handling, here we will concentrate on how handsets have and will develop to handle the problems of radio frequency signals. Such considerations apply not just to mobile phones, but also to other wireless communication systems that are being developed: computer, games and data (e.g. sensors) networking, RF identification (RFID) tags, cordless phones, etc. This bewildering range of technologies typically use the “Industrial, Scientific and Medical” (ISM) radio bands, coming under titles such as Bluetooth (2.45GHz), HIPERLAN (5.8GHz), IEEE 802.11 (WiFi, WLAN, etc., 2.45 and 5.8GHz), Zigbee (0.9 and 2.4GHz), ultra-wideband (UWB, 3.1–10.6GHz). These operate at frequencies of the same order of magnitude as cellular phones (around 1 and 2GHz), but are generally shorter range than cellular networks (10s of metres rather than kilometres). Another wireless technology, WiMax (Worldwide Interoperability for Microwave Access based on IEEE 802.16), is a longer range data communication technology compared with WLAN, aiming to deal with “last mile” problems of slow copper wire communication of telephone networks up to the doorstep. WiMax was originally designed to operate at 10–66GHz, but is more likely to be initially implemented somewhere in the 2–11GHz range (802.16–2004, e.g. 3.4GHz). The global positioning system (GPS) is another radio system, operating at 1.5GHz and 1.2GHz, but consumer use needs only reception capability.

The choice of frequency for a particular application can depend on suitability, availability and considerations of the ability of radio waves to penetrate buildings and the atmosphere. Air is practically transparent to radio waves below 10GHz, but becomes somewhat more absorbing above 10GHz (Figure 2). International, regional, national and industrial politics also have a bigger impact on development than in other electronics application sectors.

Uses (actual and speculative) of the radio spectrum beyond 10GHz include satellite TV (12–18GHz; also sub 10GHz, 4–8GHz), more WLAN, radar (3MHz–110GHz; 77GHz is proposed for auto collision avoidance systems, seen as a possible application of SiGe heterojunction bipolar transistors), systems to detect contraband materials such as illegal drugs and explosives (using, e.g., nuclear quadrupole resonance with radio frequency signals), and all-weather-landing imaging systems.

Since our concern is with silicon applications in the RF domain, we will concentrate on sub-10GHz capabilities since this is the likely area where CMOS and other Si technologies are likely to gain critical markets in the near future.

Market pressures
The two obvious market constraints are cost and size of handsets. Further, mobile network operators want to sell extra services, creating new revenue streams. The new services require more complex handsets to handle third generation (3G) and sub-3G (2.xG) systems (Figure 3) providing audio, text, picture, camera and even video capture and transmission/reception capabilities. These handsets must combine digital with RF analogue operations. Further, the first generation (1G) analogue systems have been practically non-existent for some time and the few remaining are fast being converted to digital systems.

From a manufacturing perspective, where a large proportion of the handset assembly process is handed over to third-parties (i.e. “out sourced”), it is advantageous to have as few components (both for RF and digital processing) as possible. As technology scaling allows higher frequencies to be handled, one can expect an increasing proportion of the signal processing to be carried out in the digital rather than analogue domain. Different companies will have different ideas as to which functions are “theirs” and what should be left to someone else. These choices will depend on the abilities of particular technologies – CMOS, bipolar, III-V – to handle high frequency, high power, low power loss, complex circuits and system integration, and to deliver low cost production and compressed device sizes.

No device is an island
One snag with combining digital and analogue technologies is that digital is inherently noisy since in ideal form its signals consist of step functions. In reality, of course, digital signals take a finite time to change between the two voltage states (rather than the zero time of step functions). Even so, as the clock rate determining the digital signal speed increases, a broad band of noise frequencies can be produced that can interfere with the radio section that needs precise, high power analogue operation. Interference can occur within the radio circuitry (analogueanalogue) and between the radio sections and the rest of the device (analogue-digital). This consideration is most important for highly compact mobile phone systems as opposed to WLAN in laptops and fixed system units where there is more scope for separating digital and radio components.

The International Technology Roadmap for Semiconductors (ITRS) organisation has highlighted this issue in its 2006 update document for its 2005 edition: “A signal isolation roadmap with quantitative technical requirements is very difficult because agreement on which figures of merit and measurements to use does not exist.” This may be an indication that the 2007 ITRS (due in December) will not contain signal isolation metrics as was mooted as “possible” in 2005. And that’s before actually dealing with the problem – the ITRS believes that signal isolation could be the most difficult blockade on the path to full RF systems-on-chip (SoC).

Signal isolation strategies need to consider multiple couplings: on single chips, between chips in a system package and between devices on one circuit board. On the one hand there are high RF voltages needed to give the transmission sufficient power to reach the nearest phone network base station. Power management and intermediate frequencies on the way to the “digital baseband” (i.e. the digital signals used by the device to carry out its functions) constitute further noise sources. Noise coupling can occur through the power supply, the ground terminal and through shared substrates. To reduce interference a variety of technologies and design strategies are used: high resistance substrates, appropriate interconnect and package technology, oxide isolation, buried wells, guard rings, signal filters to massage the spectral distribution into a less noisy form, etc. One future development may be the need to integrate special shielding structures into devices. Such structures would likely need new materials that would have to go through extensive matching with existing and future process technologies.

Process of choice
Given the pressures for low-cost, high-integration, one naturally turns to CMOS. Traditionally, the disadvantage of CMOS has been lower performance, particularly for high precision analogue and high voltage circuits. Just a couple of years ago, when the ITRS for 2005 was being written, bipolar CMOS (BiCMOS) was the dominant technology for producing RF transceivers in cell phone handsets, while CMOS systems were used for the shorter range needs of WLAN. Since then, Texas Instruments has integrated its RF transceiver into its OMAPV1035 multimedia digital baseband and applications processor chip (Figure 4). Similarly, Broadcom’s 65nm BCM21331 single-chip EDGE/GPRS/GSM multimedia baseband processor comes with fully integrated RF transceiver and audio for stereo music. Now, CMOS transceivers are being touted even for 3.5G systems such as HSDPA (high-speed downlink packet access) and WCDMA. The disadvantages of BiCMOS are the need for extra processing steps to integrate bipolar devices, leading to higher cost, and lower density of functions.

On the other hand, although Silicon Laboratories developed a standard CMOS-based RF power amplifier and even achieved a handset design win with a Chinese manufacturer, GaAs devices continue to dominate this area given their superior power density/efficiency allowing smaller board footprints. The sale of Silicon Laboratories’ PA line to NXP (the company formerly known as Philips Semiconductors) in March 2007 could either indicate that the product was failing to find a market or that NXP made Silicon Laboratories an offer it couldn’t refuse. TI’s OMAPV1035 and Broadcom’s BCM21331 leave off the PA function for someone else to handle.

These moves reflect the increasing capability of CMOS with scaling and improvements in design technology. Scaling improvements give benefit in terms of conserving battery power, frequency performance, circuit complexity and integration. In addition, design tools are now better able to handle RF, precision analogue and mixed-signal (analogue-digital and digitalanalogue conversion) combined with the easy stuff (i.e. pure digital).

However, it is not known how the coming material changes necessitated by continued scaling (given shrinking oxide thickness to the atomic scale) will impact RF chip design. First off will be the change to high-k dielectric to allow a thicker gate insulation layer and the simultaneous change from polysilicon to metal for the gate electrode. Intel and a consortium of companies working at Sematech claim to have separately solved the problem for the NMOS and PMOS sides of the complementary metal-oxide-semiconductor (CMOS) high-k gate insulator, metal gate electrode process. Intel has already implemented its high-k/metal combination to produce a demonstration 45nm microprocessor. The process is being developed at Intel’s Oregon D1D 300mm wafer development facility and implementation at other sites is due to begin later this year (Fab 32, Arizona, and Fab 28 in Israel in 2008). However, microprocessors are digital devices and CMOS for cell phones will require better knowledge and control of threshold voltages, current mismatches and 1/f noise.

Further down the line is the need for higher mobility channels. Traditional scaling requires increased channel doping to maintain performance. However, an assumption of the scaling formula is that the ability of electric fields to move carriers in the channel (the mobility coefficient) remains constant. This is not true. Beyond doping concentrations of 1016/cm3, the mobility of silicon falls off sharply.

Strain induced by buried layers of silicon germanium is one way that has been used to mitigate this problem. Some research has begun on using higher mobility materials such as indium antimonide (InSb), a “III-V” material, as is being developed by collaboration between Intel and the UK (largely defence) research company Qinetiq. Another proposal is to use a fullydepleted structure built in thin silicon on insulator layers that are not intentionally doped to restore the natural mobility of silicon (due 2010 according to ITRS 2006 update).

Double or even triple gates are also proposed to improve transistor performance (~2011 in ITRS 2006). The multi gate structure is expected to continue scaling up to 2020. The US Semiconductor Research Corporation has launched a project on using III-V material channels, hoping to implement the technology in the 2012–14 timeframe, although the ITRS has a more conservative 2016–19. How these will impact on the cell phone derived mobile devices that will be around at that time is anyone’s guess.

Passive aggression
A final aspect that usually gets lost in digital applications is the need to integrate passive devices – resistors, capacitors and inductors. These components are used to match impedances (ensuring low loss transmission of signals between different parts of a circuit), create resonance and filter circuits, and adjust biases. These circuits constitute vital components of low-noise amplifiers, voltage controlled oscillators (VCO, Figure 5), signal mixers and power amplifiers. The VCO, in particular, can be difficult to integrate into CMOS due to critical parameters such as the need for a large tuning frequency range, low power consumption and low phase noise. At the centre of the VCO is an LC (inductor-capacitor) ‘tank’ circuit that is determined by passive performance.

Passives should have behaviours as close as possible to ideal – capacitors should not allow leakage and inductors should be of low resistance for low power loss. In addition, the tolerances for passive components in analogue and analogue-to-digital conversion applications are usually much tighter since one is interested in more than just the two voltage levels of digital circuits. At radio frequencies interconnections also act far more like transmission lines with their own capacitance, inductance and resistance effects. Temperature and voltage dependence of passive components are further important considerations.

While the trend is to move passive devices from board to chip, integration can involve extra processing and non-standard materials and, in RF circuits, may take up more area than the active (transistor) devices that provide the amplification and switching functions. Already, high-k dielectrics are used to compress the size of capacitors in dynamic random access memory (DRAM). Passives may be integrated at the transistor level (front end of line) or in the metal layers (back end of line). Another option is to integrate passive devices into chip or module packaging rather than separately applying them to circuit boards. Cost and production simplification are again key considerations in the choices to be made.

Unlike the situation for transistor performance, scaling usually impacts badly on passive devices. Particularly difficult to integrate is high-Q (i.e. low power loss) inductance. High Q behaviour requires low resistance wiring, but resistance increases with the thinner wiring of deep submicron and nanoscale devices. Parasitic effects in inductors include magnetically induced eddy currents in the silicon substrate, leading to further power loss, and capacitive couplings that can also develop.

CMOS inductors are generally integrated into the last, thickest layer of metal using thick via connections and thick insulation from the substrate to reduce such effects. Since inductance depends on magnetism, special magnetic materials could be useful in boosting inductance values or for creating shields for reducing parasitic effects. However, such materials have to be such that they don’t affect other devices or the processing as a whole. Thick aluminium and copper inductors can achieve Q values of 25–30 for 1nH devices operating at 3–5GHz.

Further, one may stack inductors above the finished chip (i.e. above the passivation level). The disadvantage is the need for extra post-processing steps. Researchers at the European IMEC organisation have worked on above-chip passives such as high-Q inductors (Figure 6). Q-factors above 40 at 4.7GHz have been measured for a 1.8nH inductor with a resonance frequency of 2GHz.Finally, for the most demanding applications one may need external inductors, possibly incorporated into device or module packaging, or even at the circuit board level. Of course, all these special solutions to the inductance problem add significant costs to the base CMOS process.

A particularly important component for radio frequency tuning is the voltage controlled variable capacitor, also known as a varactor. One such device is a reverse-biased diode, but its performance leaves much to be desired. Another component that can be used to vary capacitance is a series of MOS transistors (MOS varactor). Here, one is looking for a wide tuning range and high Q. In some good news, the ITRS for 2005 reported that MOS varactors had achieved higher tuning ranges than expected in a scaled format. The effect of high-k materials on MOS varactors should be positive. Q factors need to be improved for future highly scaled devices or this could become the dominant limiter for VCO performance as opposed to inductor performance.

Although the remaining devices (fixed value capacitors and resistors) have a longer history and a simpler implementation in CMOS, there are challenges even here. Capacitors can be introduced in a MOS transistor-like structure (without the source or drain) giving a MOS capacitor or in the metal layers giving the metal-insulator metal (MIM) or metal-oxide-metal capacitors. MOS capacitors suffer the same leakage problems as transistors and high-k is likely to be effective at both reducing this and increasing capacitance density for both MOS and MIM capacitors. However, MIM capacitors require extra processing steps while MOM capacitors have mismatch problems.

For resistors, one is looking for low parasitic capacitance and temperature linearity. Increasing process complexity for highly scaled devices makes FEOL resistors constructed from p-doped polysilicon more difficult to produce, particularly to the tight tolerances needed for RF. Thin-film BEOL resistors (e.g., constructed of TaN as used in copper wiring schemes) can suffer from electromigration problems degrading the performance of wiring as a result of heating of the passive device structure.