Photovoltaics

Efficient thin-film silicon solar cells show linear increase over time

The price of photovoltaic electricity could be substantially lowered by producing solar cells from polycrystalline-silicon (pc-Si) thin films deposited on cheap substrates. Here IMEC scientists, Koen Snoeckx, Ivan Gordon, Guy Beaucarne, and Jef Poortmans illustrate the potential for thin-film pc-Si cells based on aluminum-induced crystallisation (AIC) and thermal chemical-vapour deposition (CVD).

In the photovoltaic industry, wafer-based crystalline Si technology still dominates the market with a share of more than 90%. A substantial part of the existing cost of solar cells however is taken up by the price of the silicon base material. A silicon thin-film technology could therefore lead to cheaper modules since they use less silicon. The basic idea would be to exploit the low-cost potential of thin-films without losing the high-efficiency of crystalline Si. As films with larger grain sizes contain less grain boundaries, which negatively influence the electronic quality, a technology with grain sizes between 1µm and 1mm seems particularly promising. Already state-of-the art pc-Si mini-modules with efficiencies close to 10% and an open-circuit voltage around 500mV have been demonstrated in scientific literature. These cells are based on solid-phase crystallisation (SPC), leading to typical grain sizes of 1-2µm. By using an AIC seed layer and epitaxial thickening, however, grain sizes in the range of 5-20µm can be obtained, which in the end can turn out to be more beneficial.

8% cell
Based on AlC of amorphous silicon on alumina substrates and thermal CVD for epitaxial growth, IMEC has built a strong know-how in thin-film pc- Si solar cell research. A number of improvements to this basic process concept have allowed going from 1.5% efficient cells to cells with 8% efficiency in less than four years time. [Figure 1] Most important adjustments contributing to this evolution were the use of spin-on oxides to smooth the surface of the alumina substrate, the application of heterojunction emitters instead of classical diffused emitters, the pattern and position of the metal contacts and the texturing of the cell surface.

The substrate
As already mentioned, the grain size of the active pc-Si layer has a capital influence on the final characteristics of the cell. To obtain as little nucleation centres as possible for the AIC process, the alumina substrate therefore has to be as smooth as possible. By using a single layer of spinon oxides, the root mean square (RMS) roughness of the alumina can be reduced from 130nm to around 45nm, which is almost a factor three improvement. Average grain sizes thereby increase from around 1µm on bare alumina to around 5µm for surfaces covered by a spin-on oxide. Figure 2

The effect on the electrical characteristics of the cells is considerable. While the short-circuit density stays more or less the same, the open circuit voltage (Voc) increased from 377mV to 424mV. The fill factor increased from 55% to 61% and the energy conversion efficiency relatively increased with 30%.

By applying multiple layers of spin-on oxide, the surface roughness can even further be reduced – thus grain sizes increased – and indications exist that this can even further enhance the electrical parameters.

Also, the use of glass-ceramic substrates instead of alumina might have the same effect. Recent results indicate Voc values up to 539mV on glassceramic substrates, without the use of spin-on oxides. Although all results discussed further are obtained on alumina, glass-ceramics might be a valuable alternative.

The contacts
Since high temperature CVD is used for the epitaxial thickening of the pc-Si, one cannot use a conductive intermediate layer between the substrate and the active layer as in other thin-film technologies. Indeed, those layers (e.g. SnO or a Mo layer) are either temperature-sensitive or lead to contamination at high temperatures. The process is therefore not compatible with the use of a back contact between the insulating alumina substrate and the pc-Si layer. Instead, a dedicated contact scheme was developed. It consists of an interdigitated pattern of base and emitter contacts on top of the cell. Figure 3

The interdigitated contact scheme leads to excellent results. Thanks to the low series resistance (0.7Ohm cm2), fill factors were always between 70-75%.

The Junction
In the course of the cell development, a major change in the cell structure was introduced by going from classical homojunction emitters to lowtemperature heterojunction emitters.

The heterojunctions were formed by deposition of thin double layers of undoped and P-doped amorphous silicon using plasma-enhanced CVD at 180°C. The optimal thickness on the pc-Si layers appeared to be around 15nm. As a comparison, homojunctions were made by phosphorous diffusion at 860°C, typically resulting in emitters of around 300nm thick.

For both options, plasma hydrogenation was done at 400°C, but at a different moment in the process flow. The heterojunction cells are hydrogenated before emitter deposition, while the homojunction cells are treated after emitter diffusion. This shift was necessary since the amorphous silicon used for heterojunctions degrades at temperatures above 200°C.

The cells with heterojunction emitters score significantly better in terms of Voc. While the short-circuit density (Jsc) after both approaches is similar, the Voc of the heterojuncion cells is typically 60-70mV higher, independent of the cell thickness and the pattern of the contacts. The improvement most likely results from a better bulk passivation and the absence of preferential diffusion. In homojunction cells, preferential diffusion along grain boundaries causes P-doped spikes. Such emitter spikes extend deep into the absorber layer, thereby increasing the effective junction area and leading to more space-charge recombination (thus lower Voc). It was observed that the final Voc increased with decreasing the cell thickness, as is expected for devices with very low diffusion length in the base. By limiting the cell thickness to 2µm, heterojunction cells with a Voc up to 536mV were demonstrated. Because of this large potential, IMEC incorporated the heterojunction emitters in the standard cell process, as a replacement of the diffused emitters.

The surface
To improve the Jsc, of the p-Si solar cells, a plasma texturing process was developed to lower the front-surface reflection and obtain an oblique coupling of incident light. Although the alumina substrate can be seen as a diffuse back reflector, the Jsc of untextured cells remains relatively low (around 17mA/cm2), due to the small thickness of the absorber layer. After plasma texturing however, the Jsc rises with roughly 15% to almost 20mA/cm2.

For the texturing, classical chemical methods such as anisotropic etching with NOH or KOH solutions or acidic isotropic etching are not applicable, since they remove too much material from the thin active pc-Si layer. The plasmatexturing optimized by IMEC only removes around 1µm of this layer. After treatment, the surface roughness is considerably higher (Figure 4) and the reflectance drops from around 35% to merely 15%. Moreover, the reflectance after texturing is almost completely diffuse, while the as-grown layers show a large specular component in the reflectance. Besides these advantages, the plasma texturing also contributed to a small increase in Voc and enhanced the external quantum efficiency (EQE), especially at short wavelengths. The fact that cell efficiency increases from 5.7% to 7.0% with the plasma texturing as the only differentiator, indicates the importance of this process step. An important note is that the positive effect of the texturing on Jsc diminishes – or even becomes a negative effect – when the thickness of the back surface field (BSF) layer exceeds 0.5µm. In IMEC’s process flow, the BSF is formed during epitaxial CVD by a highly doped p+-Si layer on top of which the actual p-doped absorber layer is grown. For the best results, the thickness has to be optimized and should not exceed 0.5µm.

Future Outlook
To ensure that the linear trends that is observed in IMEC’s technology for thin-film pc-Si solar cells is maintained, even more new features will have to be incorporated in the process. One of the routes under investigation is the use of transparent glassceramic substrates as an alternative for the alumina. In the near future, this will allow making cells in a superstrate configuration, leading to an increase in current density and lower resistive losses. Another observation is that the absorber layers in the current process flow still contain a large number of electrically active intra-grain defects. To further increase the pc-Si cell efficiency, improving the intra-grain quality by reducing the intragrain defect density will be an important element. The IMEC research in this domain is partly funded by the EU projects METEOR and ATHLET.