News Article
SEMATECH and UCL identify charge-trapping mechanism in novel materials for advanced gate stacks in new generation of transistors
Researchers at SEMATECH and University College London (UCL) have identified a potential cause of a perplexing tendency of novel dielectric materials to capture electrons and holes, making the performance of advanced devices unstable.
Researchers at SEMATECH and University College London (UCL) have identified a potential cause of a perplexing tendency of novel dielectric materials to capture electrons and holes, making the performance of advanced devices unstable. In a paper published by Physical Review Letters, UCL and SEMATECH scientists predict that the existence of hole and electron polarons in key dielectric materials may be more common than currently assumed.
A polaron is an electron, polarising the surrounding atomic lattice in a way that it creates a potential well for its localisation. "This new understanding of the polaron-formation properties of the transition metal oxides opens interesting possibilities for mitigating these undesirable material characteristics and hopefully will stimulate further research on the polaronic features in high-k dielectrics" said Gennadi Bersuker, a SEMATECH Fellow and one of the paper's authors.
New materials exhibiting high dielectric constants have attracted tremendous interest from engineers and scientists striving to use high-k dielectrics for advanced semiconductor transistors. However, one of the major obstacles to the practical introduction of these materials is their ability to capture electrons and holes, causing a device's performance to become unstable. Most scientists have long believed that these charge-trapping properties originate from the structural imperfections in the high-k dielectrics themselves. Based on this understanding, significant efforts were devoted to improving material stoichiometry. However, as was theoretically demonstrated in this publication, the charge trapping may also occur in the structurally perfect materials, since both electrons and holes may experience self-trapping by forming polarons in the highly polarisable high-k dielectric, such as HfO2. In this case, "The interaction of an electron or hole with the perfect lattice creates a potential well that traps the charge, just as a deformation of a thin rubber film would trap a billiard ball," explained Prof. Alexander Shluger of UCL.
The resulting prediction that at low temperatures electron and holes in these materials can move by hopping between trapping sites, rather than propagating as a wave, can have important practical implications for their electrical properties. For the first time, Prof. Shluger noted, theoretical modeling provided a direct look inside polaron structure in a transition metal oxides, indicating that electron and hole localisation as polarons can be a defining characteristic of such materials SEMATECH has been at the forefront of advanced transistor development, demonstrating high-k/metal gate stacks that can be used to build high-performance nMOS and pMOS transistors in a CMOS configuration. This new understanding has helped clear a path to building advanced high-k gate stacks, and prepared the way for a new era in which future transistor scaling is dominated by heterogeneous integration of novel dielectric and semiconductor materials.
A polaron is an electron, polarising the surrounding atomic lattice in a way that it creates a potential well for its localisation. "This new understanding of the polaron-formation properties of the transition metal oxides opens interesting possibilities for mitigating these undesirable material characteristics and hopefully will stimulate further research on the polaronic features in high-k dielectrics" said Gennadi Bersuker, a SEMATECH Fellow and one of the paper's authors.
New materials exhibiting high dielectric constants have attracted tremendous interest from engineers and scientists striving to use high-k dielectrics for advanced semiconductor transistors. However, one of the major obstacles to the practical introduction of these materials is their ability to capture electrons and holes, causing a device's performance to become unstable. Most scientists have long believed that these charge-trapping properties originate from the structural imperfections in the high-k dielectrics themselves. Based on this understanding, significant efforts were devoted to improving material stoichiometry. However, as was theoretically demonstrated in this publication, the charge trapping may also occur in the structurally perfect materials, since both electrons and holes may experience self-trapping by forming polarons in the highly polarisable high-k dielectric, such as HfO2. In this case, "The interaction of an electron or hole with the perfect lattice creates a potential well that traps the charge, just as a deformation of a thin rubber film would trap a billiard ball," explained Prof. Alexander Shluger of UCL.
The resulting prediction that at low temperatures electron and holes in these materials can move by hopping between trapping sites, rather than propagating as a wave, can have important practical implications for their electrical properties. For the first time, Prof. Shluger noted, theoretical modeling provided a direct look inside polaron structure in a transition metal oxides, indicating that electron and hole localisation as polarons can be a defining characteristic of such materials SEMATECH has been at the forefront of advanced transistor development, demonstrating high-k/metal gate stacks that can be used to build high-performance nMOS and pMOS transistors in a CMOS configuration. This new understanding has helped clear a path to building advanced high-k gate stacks, and prepared the way for a new era in which future transistor scaling is dominated by heterogeneous integration of novel dielectric and semiconductor materials.
