News Article
Toshiba Validates Imprint Lithography for 22-nm Node CMOS Device Fabrication
Molecular Imprints, Inc. (MII) has announced that Toshiba Semiconductor Company, a global leader in the development and manufacturing of powerful semiconductor devices, has validated the use of MII's imprint lithography technology in developing 22-nm node CMOS devices.
Molecular Imprints, Inc. (MII) has announced that Toshiba Semiconductor Company, a global leader in the development and manufacturing of powerful semiconductor devices, has validated the use of MII's imprint lithography technology in developing 22-nm node CMOS devices.
Toshiba fabricated narrow trench features at dimensions down to 18 nm using MII's Imprio(R) 250 system. Toshiba presented its findings in a paper titled ‘Nanoimprint Applications Toward22-nm Node CMOS Devices’ at the 33rd International Conference on Micro- and Nano-Engineering (MNE) in Copenhagen, Denmark.
Results detailed in the paper demonstrate the process capability and stability of MII's Step and Flash Imprint Lithography (S-FIL(R)) technology for next-generation semiconductor manufacturing. Significant enhancements over earlier performance in the areas of imaging, defectivity and overlay control were confirmed. Specifically, Toshiba leveraged MII's Imprio 250 system to pattern 18-nm isolated features and 24-nm dense features with <1-nm critical dimension uniformity (CDU) and <2-nm line edge roughness (LER). Defectivity levels of as low as <0.3 defects per cm squared were achieved, which are approaching those of immersion lithography. Device overlay results were also within Toshiba's required specifications.
Toshiba fabricated narrow trench features at dimensions down to 18 nm using MII's Imprio(R) 250 system. Toshiba presented its findings in a paper titled ‘Nanoimprint Applications Toward22-nm Node CMOS Devices’ at the 33rd International Conference on Micro- and Nano-Engineering (MNE) in Copenhagen, Denmark.
Results detailed in the paper demonstrate the process capability and stability of MII's Step and Flash Imprint Lithography (S-FIL(R)) technology for next-generation semiconductor manufacturing. Significant enhancements over earlier performance in the areas of imaging, defectivity and overlay control were confirmed. Specifically, Toshiba leveraged MII's Imprio 250 system to pattern 18-nm isolated features and 24-nm dense features with <1-nm critical dimension uniformity (CDU) and <2-nm line edge roughness (LER). Defectivity levels of as low as <0.3 defects per cm squared were achieved, which are approaching those of immersion lithography. Device overlay results were also within Toshiba's required specifications.
