IMEC extends sub-32-nm research
IMEC has announced two separate steps forward on research aimed at pushing chip technology to 32-nm and below. It has launched research on next-generation DRAM metal-insulator-metal capacitors (MIMCAP) process technology as part of its (sub-)32nm CMOS device scaling program, which it says will allow it and its partners to address the material and integration requirements to scale DRAM MIMCAP to future technology generations.
In order to scale DRAM towards the 50-nm node and beyond, MIMCAP dielectrics require materials with a higher dielectric constant compared to current industrial materials, IMEC said. By mid 2008, an effective oxide thickness of 0.5-nm is targeted for the MIMCAP dielectric in the sub-50nm technology node, going down to 0.3-nm in 2009 for the sub-45-nm node. IMEC said that scaling the dielectric equivalent oxide thickness while attaining very low leakage currents is one of the major bottlenecks DRAM industry is facing; the center said its program is addressing this challenge.
The DRAM MIMCAP sub-program is part of the CMOS device scaling program within IMEC's (sub-)32nm CMOS research platform.
