News Article
IMEC and Georgia Tech seek partners for packaging interconnect
The Microsystems Packaging Research Center (PRC) at the Georgia Institute of Technology in Atlanta and IMEC have invited interested parties from global industry to join their advanced research program on next-generation flip-chip and substrate technology.
The Microsystems Packaging Research Center (PRC) at the Georgia Institute of Technology in Atlanta and IMEC have invited interested parties from global industry to join their advanced research program on next-generation flip-chip and substrate technology. The program addresses the key ‘IC-to-package to board' packaging interconnect issues for 32nm ICs and beyond.
Building on their complementary capabilities, IMEC and Georgia Tech have joined forces by setting up an industrial affiliation programme to solve the packaging interconnect gap. Together with their industrial parties, they will explore, develop and invent new solutions to interconnect high-density ICs with very tight I/O pitches (down to 40-20µm peripheral) to low-cost packages and printed circuit boards. The programme targets novel packaging approaches to reduce the mechanical stress on the IC after packaging and assembly. These low-stress packaging techniques become indispensable when using Cu/low-k on-chip interconnections, since low-k materials typically have very weak mechanical properties.
The program will provide solutions for the four major barriers to next-generation flip-chip packaging of scaled ICs and ultra-low-k dielectric ICs. Its aim is to explore and develop:
1. Organic package interposer substrates that minimise stress at die and package level and enhance the wiring density, the fine I/O pitch routing capability and the high-frequency signal performance of substrates;
2. A new generation of fine-pitch flip-chip UBM (under-bump metallisation) and barrier metallisation that meet the electromigration and thermo-mechanical reliability targets of flip-chip scaling;
3. Novel solder and non-solder interconnect approaches including advanced underfill materials and processes to meet future current density, geometry and reliability requirements;
4. Thermo-mechanical modeling, design and verification for improved reliability.
The two-year program is open for the entire supply chain including system companies, IC manufacturers and assembly houses. Partners can benefit from the complementary expertise of the PRC, a global leader and pioneer in package and system integration, and IMEC, a pioneer of silicon-centric technologies. The extensive state-of-the-art facilities for packaging and semiconductor processing, fabrication and integration at both institutes are major assets of this program.
Building on their complementary capabilities, IMEC and Georgia Tech have joined forces by setting up an industrial affiliation programme to solve the packaging interconnect gap. Together with their industrial parties, they will explore, develop and invent new solutions to interconnect high-density ICs with very tight I/O pitches (down to 40-20µm peripheral) to low-cost packages and printed circuit boards. The programme targets novel packaging approaches to reduce the mechanical stress on the IC after packaging and assembly. These low-stress packaging techniques become indispensable when using Cu/low-k on-chip interconnections, since low-k materials typically have very weak mechanical properties.
The program will provide solutions for the four major barriers to next-generation flip-chip packaging of scaled ICs and ultra-low-k dielectric ICs. Its aim is to explore and develop:
1. Organic package interposer substrates that minimise stress at die and package level and enhance the wiring density, the fine I/O pitch routing capability and the high-frequency signal performance of substrates;
2. A new generation of fine-pitch flip-chip UBM (under-bump metallisation) and barrier metallisation that meet the electromigration and thermo-mechanical reliability targets of flip-chip scaling;
3. Novel solder and non-solder interconnect approaches including advanced underfill materials and processes to meet future current density, geometry and reliability requirements;
4. Thermo-mechanical modeling, design and verification for improved reliability.
The two-year program is open for the entire supply chain including system companies, IC manufacturers and assembly houses. Partners can benefit from the complementary expertise of the PRC, a global leader and pioneer in package and system integration, and IMEC, a pioneer of silicon-centric technologies. The extensive state-of-the-art facilities for packaging and semiconductor processing, fabrication and integration at both institutes are major assets of this program.
