Technology options for lithography at 32nm
There are three technology candidates for 32nm lithography: increasing the Numerical Apertures (NA) for 193nm lithography using a high-index immersion liquid, reducing the wavelength of the exposure tool to 13.5nm by transitioning to extreme ultraviolet (EUV), or using hyper-NA 193nm water immersion with double-patterning (splitting the circuit pattern into two lower resolution patterns that are then individually printed and processed). High index immersion is technically feasible, but is a single-node solution that cannot be ready in time for general acceptance. EUV can support multiple generations with single-exposure lithography, but will not be a mature technology for several years. Even though there are issues to be solved, double-patterning techniques are likely to be used as a bridge technology between today’s ArF immersion scanners addressing the 45nm node, and the mature EUV volume manufacturing tools of the future.
Industry continues IC scaling
IC manufacturers continuously shrink the design rules used for chip manufacturing. Printing smaller features allows memory makers to reduce the silicon wafer area (and hence the cost) required for the same memory capacity, or to increase the memory capacity of the same die size. While the benefits of scaling are obvious for pure memory devices, it is important to note that the memory content of many advanced logic ICs, such as DSPs and microprocessors, can occupy 50% or more of the die area, so the scaling benefits of reduced area and expanded memory are just as applicable.
Driven by market opportunity, and the scalability of its device structure, NAND flash is leading the shrink to smaller resolutions, as illustrated in Figure 1, which summarises the rate at which 14 major IC makers have introduced new device geometries to volume manufacturing.
Resolution is not the only critical lithography parameter that determines the scaling of ICs. For DRAM devices, the tolerances for how accurately device pattern layers must be overlaid above previous layers is also a critical factor in minimising the cell area. This is illustrated in Figure 2, which shows the typical overlay design rule requirements for different devices as a function of their minimum feature resolution. The step function change shown in overlay requirements for DRAM is driven by the migration from cell designs with an area of eight times the square of the minimum feature size, 8F2, to six times the square of the minimum feature size, 6F2.
Lithography solutions to enable continued scaling
The resolution of optical lithography systems is described by the Rayleigh equation, R = k1 l / NA, where k1 is a proportionality factor that has a limiting value of 0.25 for a single exposure, l is the wavelength of the light and NA is the numerical aperture of the optics (1). Typically as k1 decreases, contrast is lost in the image. Resolution enhancement technology (RET) techniques have evolved to bring back contrast even as device half pitch has continued to shrink. Commonly used RETs include off-axis illumination, the use of phase-shifting masks, and the addition of sub-resolution assist features to mask features (2).
Immersion lithography using hyper-NA water-immersion scanners operating at 1.35NA and a 193nm wavelength enables production down to 40nm half pitch at a k1 of 0.27. Further extension of 193nm immersion to 32nm is not possible with single patterning, however, because the required k1 is below the diffraction limit of 0.25, and a further increase in NA is limited by the refractive index of water of 1.436 at 193nm wavelength.
As the Rayleigh equation suggests, there are three ways to improve optical resolution:
1) increase NA, 2) decrease wavelength, or 3) decrease k1. Figure 3 summarises the NA, wavelength, and k1 for optical lithography used in production of recent devices, as well as the main alternatives for continued device scaling to 32nm half pitch and beyond. Across the top of the table is the half-pitch resolution and the likely start date of production, assuming a two-year cycle. Along the vertical axis are the wavelengths and NA that have been introduced or are contemplated to address these half-pitch nodes. Along the diagonal are the corresponding k1 values.
The roadmap suggests three main technology options for extending lithography to 32nm half pitch:
● continue to increase NA at the 193nm wavelength using higher-index fluids and glass materials (4) or
● use the existing NA and wavelengths, but extend the effective k1 beyond the diffraction limit by applying double patterning (5) or
● scale the wavelength to 13.5nm, using EUV light sources and reflective reduction optics in a vacuum environment (6).
The following sections will discuss each of these three alternatives.
Alternative # 1 - Increase NA using High-Index ArF Immersion.
Increasing NA further by using high-index immersion fluids and optical materials could allow the industry to re-use some infrastructure elements already in place for 193nm lithography, such as reticles and laser sources. However, developing new glass materials that meet all the optical requirements, and possess the necessary higher refractive index, poses significant technical and economic challenges. Moreover, suitable quantities of glass with the required quality are not expected to be available before 2010. This pushes the realisation of high-index 193nm lithography beyond the timing required by leading customers for production below 45nm, especially for applications such as NAND flash.
In addition to the new glass, a new fluid is also needed. Most of the fluids with sufficiently high-index exhibit high viscosity (i.e. show a large resistance to deform under shear stress), which will require significant changes to the fluid handling in exposure tools. Furthermore, none of the ArF resists in use today have been developed with these new fluids in mind, so it is likely that a new learning cycle will be needed to drive down defect levels. In addition, these fluids tend to be toxic and expensive, so an effective recycling strategy must be implemented.
Today’s plain-water systems require no such measures.
The capability offered by these high-index immersion systems is only usable at the 32nm node. For the next node, a new solution again would be needed. The lack of extendibility, combined with an earliest possible introduction in 2010, makes this technology option the least likely choice for mainstream lithography at the 32nm node.
Alternative #2, Lower K, with Double-Patterning
The second option, lowering the effective k1 through the use of double-patterning, is also attractive from the point of view of infrastructure re-use. In this scheme, chip patterns so dense they are beyond the Rayleigh limit of k1 0.25 are split into two or more less-dense mask patterns, each with k1 > 0.25.
In a straightforward implementation, shown in Figure 4 as dual-line double-patterning, mask 1 is exposed and etched into a hardmask film. The wafer is then coated with resist and mask 2 is aligned to the etched pattern, exposed, and then etched again. In this manner, patterning with resolution below the Rayleigh limit can be achieved.
Double-patterning, while promising the possibility of extending 193nm immersion technology to below 40nm half pitch, has many technical and economic challenges. Chief among these are:
a) the required pattern-to-pattern overlay
b) the cost impact of doubling the number of critical patterning steps and masks, and
c) the split of the device pattern into 2 separate layers.
This technique lends itself much more readily to the production of NAND flash, due to its simple periodic patterns.
An alternative double-patterning approach uses spacer technology to form self-aligned structures at sub-resolution feature size (7). Compared to a dual-line double-patterning process, spacer technology reduces the likelihood of overlay and mask registration errors, but requires even finer critical dimension (CD) control. It also significantly increases the number of deposition and etch steps required, with significant impacts on processing cost and cycle time. Spacer double-patterning (as shown in Figure 4) is most likely a candidate only for fabrication of NAND flash devices.
In Table 1, the CD control, overlay error (each expressed as a percentage of the design rule), and number of processing steps for single-exposure lithography technology are compared to the specifications required for litho double-patterning and spacer double-patterning. Each approach has tradeoffs. But all versions of double-patterning will require longer cycle times through the wafer fab than standard single-exposure lithography.
Alternative #3, Reduce l with EUV Lithography
Reduced wavelength has been a key enabler in extending the resolution of optical lithography, with transitions from 436 nm to 365 nm to 248 nm and, most recently, to 193nm. EUV’s 13.5nm wavelength, which is about 15x shorter than the industry’s current 193nm wavelength, will significantly extend resolution at moderate NA and high k1 values, and offers the potential to further extending resolution to several additional generations of device design rules with cycles of learning.
EUV is attractive, in part, because it offers many of the same benefits as traditional optical lithography: resolution that scales with aperture and illumination, illumination power at the wafer that scales with source power and system transmission efficiency for high throughput, the absence of charged-particle interaction issues that can occur with electron-beam lithography, which limit the charge density, current, and throughput, and rigid masks at 4x reduction, which can be patterned much like optical today’s masks.
EUV, as a single-exposure technology, offers the additional benefits of improved CD control, ‘relaxed’ overlay, binary masks with minimal need for RET, and reduced processing, as summarised in Table 1. Together, these advantages should result in better manufacturing cycle time and lower overall cost per layer than any of the other technology options for 32nm and beyond.
EUV infrastructure still requires significant development to reach the maturity level required for high-volume production, and this is likely to delay the use of EUV in IC manufacturing. Although significant progress has been made, key challenges remain: 2x improvement in source power to support > 100 wafer/hour throughput,3x reduction in line-width roughness of chemically amplified resists that have a dose sensitivity of 10mJ/cm2, andmaturity of mask fabrication and metrology, including the production of reflective mask substrates with < 50nm flatness and essentially zero defects, and the availability of actinic inspection for defect-repair verification.
The pace of EUV development has accelerated with the 2006 shipment of the first two full-field 0.25 NA EUV alpha demo tools to research consortia in Europe and North America. Preliminary imaging from these tools, shown in Figure 5, illustrates the promise of EUV lithography. These research systems will be used to further characterise the imaging potential of EUV, while providing valuable system knowledge on vacuum-based lithography. Development has started on second-generation EUV systems for pre-production. But while they are scheduled to ship in 2009, their use in volume production will depend upon the maturity of the rest of the EUV infrastructure. In the meantime, ArF lithography is likely to be extended with double-patterning techniques to bridge the gap for leading-edge devices until EUV reaches sufficient maturity for its potential cost benefits to be realised in volume production.
Conclusions
IC manufacturers continue to aggressively pursue design rule shrinks, driven by the benefits of reduced die cost and increased IC functionality. Lithography is the main driver of shrink, with current feature resolutions now reaching below 40nm half pitch. Overlay requirements continue to tighten, however, scaling at least linearly along with resolution.
Increased NA beyond ~1.35 using high-index fluids and glass is feasible, but is challenged by the need to mature new optical materials and immersion fluids, as well as by limited extendibility and the expected late availability of applications for leading device manufacturers. During the 2008-09 timeframe, extending ArF lithography with double-patterning techniques to reduce k1 below 0.25 is expected to be the only technology available for volume manufacturing at sub-40nm resolution. Double-patterning is relatively straightforward to apply to the highly repetitive patterns of NAND flash devices, but is more difficult for the complex patterns encountered with DRAM and logic devices, where the tighter tolerances for overlay and CD may affect the scaling efficiency.
In the long term, wavelength reduction with EUV is the preferred technology for volume manufacturing of devices beyond 32nm. Though not yet ready for volume production, EUV appears likely to offer significant cost and cycle-time advantages over the interim technology of double-patterning. That potential is driving broad collaboration to mature the light source, mask and resist infrastructure for this promising next-generation optical lithography technology.
