SOI to Replace Bulk Silicon

To date, SOI has been used successfully, primarily by leading integrated device manufacturers (IDMs) who develop custom designs or their own physical intellectual property (IP) internally. SOI projects are now underway in major IDMs and foundries worldwide, with central processing units (CPUs), gaming processors and networking processors in volume production.

Basics of SOI
SOI replaces traditional bulk silicon starting wafers with an ‘engineered’ substrate consisting of three layers:
● A thin, top layer of monocrystalline silicon upon which active circuits are formed.
● A fairly thin middle layer of insulating silicon dioxide (buried oxide or BOX).
● A very thick bottom layer of bulk silicon, which essentially provides a mechanical support for the two layers above.

There are various ways to create SOI wafers, and for many years, high-quality SOI wafers were difficult to produce in high volumes. However, in the early 1990s a layer-transfer and bonding technology called Smart Cut was pioneered and patented by the French research consortium CEA-Leti.

The performance improvement of SOI complementary metal-oxide semiconductor (CMOS) technology compared to bulk CMOS is due to the accumulation of multiple factors that lead to higher transistor drive current.

● The presence of the buried oxide strongly reduces junction capacitance below source and drain.
● Dynamic lowering (during the transitions) of the threshold voltage of the transistor due to the capacitive coupling between the body, gate and source/drain on one side, which leads to higher drive current for a given transistor geometry and Vdd.
● The absence of reverse body-source bias in stacked transistor gates on the other side (Vbs=0 for SOI while Vbs=-Vdd for bulk).

Also, in SOI–based chips, transistors are fully isolated from each other and from the bulk silicon substrate underneath (Fig. 1.), which allow for simplification and shrinkage of the physical design.

In the 1990s, early adopters of SOI faced challenges such as the ready availability of high-quality SOI wafers and the building of cell libraries mastering SOI-specific design issues such as history and floating body effects. Today, however, the early adopters have addressed all these issues.

The history effect caused by the floating body effect (which dynamically affects the device timing over a series of on/off cycles) is fully characterised in today’s SOI libraries, abstracting this complexity from the ASIC designer.

SOI wafer manufacturing strategies have been perfected, so the defect levels in today’s SOI wafers are on par with the industry’s best epi wafers. They are available in the full range of diameters, up to 300mm.

Performance Choices and SOI Value
SOI technology offers a different set of benefits to the traditional CMOS process; the technical value of these can translate to product differentiation and value creation. With correct optimisation, specific applications can benefit from:
● 30-40% speed improvement.
● Up to 50% reduction in power consumption.
● >10% area reduction.

Table 1 shows a summary of the technical benefits and trade-off parameters that are available when adopting SOI.

Cost-of-Ownership
A recent study 1 by the research firm Semico found that on a straight manufacturing cost basis, the 10% to 15% cost-of-ownership (COO) figure, commonly referred to in the industry, only considers the impact of wafer cost on wafer manufacturing, using a very aggressive foundry cost model as reference.

Moving further into the semiconductor manufacturing process, Semico found that once the SOI wafer is tested, the SOI COO adds only 4% to 6% to the total manufacturing cost of the good packaged devices.

SOI COO can be further improved thanks to SOI design advantages:
● Digital logic area can be reduced by 10% in SOI. This is due primarily to the fact that SOI transistors can be more densely laid out, thereby saving die area. This, of course, favourably impacts yield.
● Innovative memory design techniques can strongly reduce embedded memory area. Reduced power dissipation may allow packaging costs to decrease as the need for heat dissipation components is reduced.

Overall, the cost of an SOI chip could be cost neutral compared to bulk and, depending upon the application, may even be lower.

For Which Applications is SOI Technology Relevant?

SOI can be considered a viable option for any ASIC application where the constraints of performance, power and reliability intersect. IDM firms have adopted SOI to enable high-performance processors; this strategy is already established, for instance, in high-performance gaming and processor markets.

It is worthwhile to recognise that the increased performance capability of SOI can also be used to provide compelling power and area improvements in devices that already meet a user’s speed requirements in bulk silicon. SOI can deliver cost savings for reduced area and product improvement through power reduction.

SOI benefits clearly give the ASIC designer an increased choice of optimisation parameters, making SOI particularly advantageous for:
● Mobile applications, where battery life is at a premium and/or where radio frequency (RF) device integration is advantageous.
● Consumer electronics, for applications processors requiring higher performance, smaller form factors and savings incurred in packaging and heat management.
● Embedded markets, where the emphasis is on performance, size, power and reliability (especially under challenging conditions as found in automotive, industrial, medical and appliance markets).

In certain pad-limited ASICs, the cost benefits of adopting smaller geometry processes are no longer applicable. However, switching these designs at the same technology node from bulk to SOI can improve PPA, thereby providing additional product differentiation choices.

Moreover, SOI can deliver benefits for specialist RF and mixed-signal applications, where high-resistivity (HR) SOI wafers can be used. These benefits, coupled with the traditional benefits of SOI digital technology, make SOI an ideal platform for low-power RF systems.

Conclusion
SOI substrate technology is positioned to replace bulk silicon in many advanced applications. The technology has been validated by leading IDMs, and early issues around its manufacture and use have been addressed. As a result, SOIbased chips now represent a $12 billion/year market and about a 6% share of the global IC market, with a projected compound annual growth rate of around 40%. Along with SOI-based processors in personal computers, servers and gaming consoles, SOI is being used in applications for nano engineering, MEMS, photonics, opto-electronics, and in conjunction with III-V materials.

Cost concerns around SOI have also been addressed with its cost impact on some applications demonstrated as minimal and for other applications SOI appears to represent a neutral or even advantageous proposition. Furthermore, there is no manufacturing penalty associated with transitioning to SOI no additional equipment is required within foundries, and those that have already adopted SOI have found that their yields are similar to bulk.

Today, SOI represents a proven process technology with a very practical adoption path that also delivers important benefits for applications where processing speed, battery life, form factor or RF integration are critical. As a result, SOI is well on its way to seeing increased usage in ASIC designs, as it further moves to displace bulk silicon.

About the Authors
Jocelyne Wasselin is the vice president of marketing and business development at Soitec. She holds a Ph.D. in materials science from the Grenoble Institute of Technology. Prior to Soitec, she spent several years at Altis Semiconductor in technology program and account management. Her career began with 15 years at IBM, where she served in a variety of technical project and management positions.