TEL joins SEMATECH's 3D interconnect programme
TEL's agreement with SEMATECH, formalised at a recent signing ceremony in Tokyo, adds significant resources to SEMATECH's effort aimed atevolving the traditional copper/low-k interconnect technology tothree-dimensional chip stacking, including through-silicon vias (TSVs)as interconnects. The 3D Program, launched in 2005 with theparticipation of SEMATECH's existing member companies, was openedearlier this year to equipment and materials suppliers, fablesscompanies, chip-makers, assembly and packaging companies, and others.
3D-TSV technology requires bonding semiconductor wafers and/or dies anduses deep TSVs for interconnects. The goal of SEMATECH's program is toenable high-volume manufacturing of 3D-TSV chips by its members with anoptimum combination of cost, functionality, performance, and powerconsumption. When ready for volume manufacturing, 3D-TSV will providecost-effective ways to integrate diverse CMOS technologies, andeventually link CMOS chips with emerging technologies such asmicro-electromechanical systems (MEMS) and bio-chips.Prior to joining the 3D initiative, TEL was engaged with SEMATECH in ajoint-development program to address early development challenges in3D-TSV, including deep-silicon reactive ion etching (RIE), costmodeling, process benchmarking, standards development, and technology road mapping.
