News Article
Lithography among top challenges to Semi Industry
According to Jin Seog Choi, chief technology officer at Hynix Semiconductor Incorporated, Korea, Lithography is among the top productivity challenges facing the semiconductor industry, but packaging and testing costs are another area that must be addressed
In a panel presentation at the International Trade Partners Conference (ITPC), Choi addressed the future technologies needed to keep cost reductions on track.Starting in 2009, when NAND devices are using 30-35 nm design rules and DRAM is in the 43-48 nm range, the memory manufacturers face critical lithography choices.
Extreme ultraviolet (EUV) lithography offers a low k1 factor, but it is unclear when EUV will be ready for high-volume manufacturing. Spacer patterning technology could be used for NAND memories or double patterning lithography may be required, for both DRAM and NAND devices.
However, double patterning "has a high cost of ownership. The low throughput of double patterning is a key issue," Choi said.