News Article
Infineon and ASE to introduce New Industry Standard Package Technology
Infineon Technologies, a supplier of semiconductor and system solutions, and Advanced Semiconductor Engineering Incorporated (ASE), a semiconductor packaging and test company, have announced a partnership to introduce semiconductor packages with a higher integration level of package size with an almost infinite number of contact elements.
This new package form achieves a 30% reduction of dimension compared to conventional (lead-frame laminate) packages.
Semiconductor pattern sizes are continuously shrinking to permit the implementation of more complex and efficient semiconductor solutions. Although the chip becomes smaller, the need for adequate connection space has imposed physical constraints on package shrinkage.
Infineon has now succeeded in extending the benefits of Wafer-Level Ball Grid Array (WLB) technology, namely, cost-optimised production and enhanced performance features, by a new technology, embedded WLB (eWLB). All operations are performed highly parallel at wafer level, as with WLBs, signifying concurrent processing of all the chips on the wafer in one step. To promote these advantages, Infineon and ASE have forged a partnership uniting the technology developed by Infineon with the packaging know-how of ASE in a license model.
The eWLB technology is a forward-looking development of the WLB technology, upholding the known benefits such as small package dimensions, excellent electrical and thermal performance, and maximum connection density. However, this technology significantly increases the functionality and application spread. Due to eWLB, complex semiconductor chips such as modem and processor chips for applications in mobile communications require a high number of solder connections with standardised contact spacing to be produced with a minimal footprint. At the same time, the packages can be provided with as many solder contacts as needed. The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new, space-sensitive applications.
The new packages will be manufactured at the production sites of Infineon Technologies and at ASE under a license model. The first components are expected to be commercially available by the end of 2008.
