Design For Manufacturing

The years of ‘happy scaling’ of CMOS technology are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, impinge deeply upon the design and manufacture of future integrated circuits and systems. The ways in which the industry will need to change in order to tackle the issue of semiconductor variability is the subject of Europe’s first international Conference on the subject.

Progressive scaling of CMOS transistors, as tracked by the International Technology Roadmap for Semiconductors (ITRS) and captured in Moore’s law, has driven the phenomenal success of the semiconductor industry, delivering larger, faster, cheaper circuits.

Silicon technology is now well into the nano-CMOS era with sub 40nm MOSFETs in mass production at the current 45nm ITRS technology generation and sub-10nm transistors expected at the 22nm technology node generation, scheduled for production in less than 10 years. 4nm transistors have already been demonstrated experimentally, highlighting silicon’s potential for scaling beyond the end of the current ITRS.

It is widely recognised, however, that variability in device characteristics and the need to introduce novel device architectures represent major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. This will in turn demand revolutionary changes in the way in which future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers.

The rapid increase in intrinsic parameter fluctuations represents the most serious challenge. These fluctuations stem from the fundamental discreteness of charge and matter and the statistics of small numbers. They are fundamental, truly stochastic and cannot be eliminated by tighter process control.

The major sources of intrinsic parameter fluctuations in the present day conventional ‘bulk’ MOSFETs include random discrete dopants (Fig.1 a, b), line edge roughness (Fig. 2) and the poly silicon granularity (Fig. 3) (i). The current level of threshold voltage variability (the standard deviation of the threshold voltage) in the 65nm technology generation approaches 50mv for transistors with square geometry. Comprehensive statistical simulation of well scaled bulk MOSFETs corresponding to the ITRS prescriptions for the 45nm, 32nm and 22nm technology generations indicate that the threshold voltage variability will increase rapidly and will exceed 100 at the 32nm technology generation (ii). This has becomes one of the major reasons for the insertion of thin body SOI MOSFETs, at the 32nm technology node which tolerate low channel doping concentrations and are more resistant to variability when compared with conventional MOSFETs.

While intrinsic parameter fluctuations and resultant device mismatch have so far affected only analogue design, they now challenge the power consumption, yield and reliability of digital circuits. One of the first digital ‘casualties’ is SRAM, which already occupies significant real estate in current System On Chip (SoC) devices (iii). Fig. 4 illustrates the random dopant induced variability in the ‘butterfly’ curves of SRAM sells corresponding to the 45nm technology generation. Only a large cell ratio can produce acceptable yield in the presence of fluctuations, which only serves to increase cell area and reduce the benefits of scaling. Thus, variability already causes significant circuit and system challenges at a time when design margins are shrinking, owing to lower VDD and increased transistor counts. Exponentially increasing design difficulties require novel statistical design solutions.

In addition, poor performance due to high device doping and reduced mobility, increased gate leakage current and unacceptable levels of random dopant-induced intrinsic parameter fluctuations will force the replacement of conventional MOSFETs with novel CMOS device architectures beyond the 65 nm technology node. It is expected that there will be no single replacement for conventional MOSFETs and that disparate device architectures will coexist and compete. All new device architectures require a more-or-less new design approach, altering device and circuit layout and the electrical behaviour of each generation of nano-CMOS devices. This adds to the design challenges associated with increasing device and circuit variability.

The statistical nature of intrinsic parameter fluctuations creates new challenges for design, simulation and verification. A previously deterministic design process must become statistical. For each individual gate shape, statistical simulations of a large sample of microscopically different transistors must be carried out, and 3D device simulations become 4D (the fourth dimension is the size of the statistical ensemble). At circuit simulation level, a statistical set of compact models represents each individual device and statistical circuit simulations of standard cells or circuit blocks must be performed. It remains an open question as to how the statistically simulated cell or circuit block behaviour should be captured and represented in higher-level logic or timing simulations. Such statistical design and simulation approaches can make potentially unlimited demands on computational resources.

At low and medium levels of intrinsic parameter fluctuations, one of the main design challenges will be the design and optimisation of circuits using statistical targets. For example, the typical performance/power trade-off in the design process will be replaced by a conditional performance/power trade-off, which produces a particular yield statistically. Novel probabilistic optimisation procedures will be developed and supported by the simulation strategy outlined above. High levels of intrinsic parameter fluctuations will force radical changes to the existing design process, including, supply voltage partitioning and adjustments, design redundancy, asynchronous architectures, a wider use of self-testing, self-healing and self-organisation. It will encourage the development of probabilistic computing and design styles. Asynchronous and probabilistic architectures will have to be studied and developed to cope with large-scale variations.

‘Design for Variability’ (DfV) has become a vibrant area of research and large research initiatives has been undertaken in Europe and Japan including the ‘Technology Aware Design’ programme of IMEC and the DfM&Y programme of STARC. Major EDA companies, including Synopsys, Cadence and Mentor Graphics, are updating their existing tools and are working on new tools to cope with the variability problems and which can ease the pain of statistical design.

In the UK the £5.3M flagship project in this area ‘Meeting the Design Challenges of the Nano-CMOS Electronics’ has been funded by the EPSRC in the framework of the National eScience initiative. This project brings together leading semiconductor device, circuit and system experts from academia and industry and e-Scientists with strong grid expertise. Only by working in close collaboration, in a way that is connected and resourced using state-of-the-art e-Science and Grid technology, can we understand and tackle the design complexity of nano-CMOS electronics. The University partners in this project include the Device Modelling and the Microsystems Technology groups at the University of Glasgow, the Advanced Processor Technologies group at the University of Manchester, the Electronic Systems Design Group at the University of Southampton, the Intelligent Systems group at the University of York and the Mixed-Mode Design Group at the University of Edinburgh. The e-Science and Grid technology will be provided by the National e-Science Centre run jointly by Glasgow and Edinburgh Universities and the e-Science North-West Centre at University of Manchester. Industrial partners in the project include ARM and Wolfson Microelectronics, Synopsys Freescale, National Semiconductors and Fujitsu. The project also has the support of the National Microelectronics Institute, the trade association representing the semiconductor industry in the UK and Ireland.

The project’s over-arching aim is to revolutionise existing nano-CMOS electronics research and design processes by developing the methodology and prototype technology of a nano-CMOS Design Grid. The term ‘Grid’ encompasses computing technologies that allow distributed groups to collaborate by sharing designs, simulations, workflows, data sets and computation resources.

This work will require a deep understanding of how device engineers, technologist and designers can work together to produce high quality circuits and systems using the statistical design methodology illustrated in Fig. 5. This will facilitate circuit and system design in the presence of significant variability, allow migration to new device technologies and encourage new design styles and solutions to cope with increased device variability.

Workflows will hide the complexity of the statistical simulation and verification from designers and so ease any pain and fear associated with the statistical design. Access to larger computational resources using the Grid means better statistics and closer-to-optimal designs.

Organised by the National Microelectronics Institute in collaboration with the UK Nano-CMOS project, Europe’s first international conference dedicated to the subject of semiconductor variability took place on 23rd October 2007 at the Royal College of Physicians, London.

The conference brought together major research initiatives and vendors of EDA tools, semiconductor technology and IP in order to fully analyse the global implications of the increasing variability on design and manufacture and to promote collaboration between the key players concerned.

The conference opened with a keynote address from Dr Asenov, entitled “Variability in next generation CMOS technologies and impact on Design”. This was followed by four speaker sessions:
Session 1: ‘Design Concepts’ – presentations by IMEC, University of Manchester and STARC.
Session 2: ‘Design implementation & tools’ – presentations by Mentor Graphics, Freescale and Cadence.
Session 3: ‘Semiconductor Technologies’ – presentations by IBM, Synopsys and TSMC.
Session 4: ‘IP Development & Research’ – presentation by ARM.

The speaker sessions were then followed by a panel discussion entitled, “Integration and Collaboration in the Era of Design for Variability (DfV)”.

In addition to the main conference, delegates were offered the opportunity to attend two complementary satellite events organised by Dr Asenov.

Consisting of half-day reviews, the events introduced delegates to the research highlights from two major multidisciplinary UK research projects in the fields of device, circuit and system design.

REFERENCES
(i) A. Asenov, A. R. Brown, J. H. Davies, S. Kaya and G. Slavcheva, ‘Simulation of Intrinsic Parameter Fluctuations in Decananometre and Nanometre scale MOSFETs’, IEEE Trans. on Electron Devices, Vol.50, No.9, pp.1837-1852, 2003.
(ii) G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy and A. Asenov, ‘Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs’, IEEE Trans Electron Dev. Vol. 52, pp. 3063-3070 (2006).
(iii) B. Cheng, S. Roy, G. Roy, F. Adamu-Lema and A. Asenov, ‘Impact of Intrinsic Parameter Fluctuations in Decanano MOSFETs on Yield and Functionality of SRAM Cells’, Solid-State Electronics, Vol. 49, pp.740-746, 2005.