Jean-Marc Girard, Nicolas Blasco, Christian Dussarrat, and Nathan Kemeling. Air Liquide Electronics, discuss the Chemical Vapour Deposition (CVD) and Atomic Layer Deposition (ALD) precursor chemistry for advanced gate stack and memory capacitors.
To remain on Moore’s law curve for the scaling of transistor sizes, device makers are obliged to move away from common Silicon/Silicon dioxide (Si/SiO2) technology and integrate more exotic materials. While process engineers are faced with the challenge of integrating new materials in the chips, such as high-k/metal gate (HKMG) (Ref.1,2), it is the mission of chemists to design, test and produce molecules that allow the deposition of such materials in high volume manufacturing.
The multitude of materials, applications and process constraints (for instance, thermal budget, film conformality, throughput, film electrical properties, scalability to batch and ALD capability), has generated a wave of chemical innovations and molecule customisation. Hence, a very large number of new ALD and CVD precursors are being used, evaluated or envisaged to fulfil the function of each film in a specific device. Here we essentially deal with the molecules enabling sub-55 nm DRAM capacitors and sub-65 nm CMOS transistors.
Devices and elements
The need for continued device scaling below 100nm has caused the semiconductor industry to move away from traditional elements like Si, Aluminium (Al) and Tungsten (W), and, to introduce new elements, both for dielectrics deposition and metallisation. In this section, new elements used in both DRAM and CMOS manufacturing will be discussed.
DRAM device manufacturers have been the first to integrate ‘hetero-elements’ such as Tantalum (Ta), Nobrium (Nb) and Al as oxides in capacitors, which have a k-value benefit over regular oxide/nitride. Highly conformal Aluminium Oxide (Al2O3) can be deposited by ALD with trimethylaluminium, enabling deposition on more complex structures such as HSG (Hemispherical Grain), which were introduced to increase the active surface area.
The need for further shrinkage and low EOT has recently led the memory makers to use Hafnium (Hf) and Zirconium (Zr) based high-k dielectrics, with higher k-value than Al2O3. Usually, these new elements are integrated as silicate or alumina nanolaminate. For the above DRAM capacitor devices, a MIS integration scheme with TiN metallisation is the most common structure today.
Before transitioning to super-high k materials such as STO and BST, next generation devices will ‘dope’ the current high-ks with various flavours of rare earth. (Rare Earth = Lanthanide series + Sc and Y). Neither the preferred dielectric composition nor the proper precursors have yet been decided and intense R&D by integration engineers and material suppliers is ongoing.
For the gate stack, the HKMG will be integrated as early as 45 nm in high-end devices, as exemplified by the recent announcement by IBM and INTEL. The introduction of these Hf-based High-k materials has been labelled by Gordon Moore as “the biggest change in the industry since the introduction of polysicon gate MOS transistors in the late 1960’s.”
Although a consensus has been reached on the Hf-based high-k films (HfSiO(N) and HfO(N) mostly), the metallisation scheme is diverging in material and process flow between three approaches, namely the Metal Inserted Poly Gate (MIPS), the Fully Silicided gate (FUSI) and the Replacement Gate (RPG) [Ref.3]. The three integration schemes need different deposition precursors, not only for the differences in the metal gate, but also because of the different process constraints, such as the low thermal budget constraint on the spacer deposition in the gate-first MIPS case, the conformality requirement of the HKMG films in the RPG case, or the compatibility of the metal gate with the oxide spacer deposition conditions.
For the MIPS and RPG schemes, a variety of metal gate materials are considered, either with a mid-gap metal such as TiN, or different metals on each type of transistor, with essentially Ta or Hf-based films on the NMOS and Thallium (Ti), W or Ruthenium (Ru) based films on the PMOS side.
At 32 nm, further gate oxide evolution may include either new materials such as amorphous lanthanum aluminate (LaAlO3), or improved schemes to tune the metal gate work function, for instance by capping the Hf-based high-ks with Lathium Oxide (La2O3) or like materials. In addition, CoSi and NiSi contacts from CVD sources will also prove desirable, especially for 3D gate structures (FINFET) where PVD is no longer applicable.
Prior to any deposition performance consideration, the minimum properties that a chemical precursor requires are reasonable volatility (the ‘reasonable’ notion depending on the target thickness of the film), sufficient stability to be vaporised up to a sufficient partial pressure without readily decomposing [Ref.4], and to be economically viable in pilot and HVM.
This last parameter depends upon the cost of the element in a useable form for chemical synthesis and ligand substitution (such as halides, triflates, or carbonyls), the individual cost of the reactants, and the synthesis complexity and yield. Interestingly, the metal cost can account for a very significant portion of the total cost, and hence subject the precursor pricing to wide variations due to the global metal market. For instance, the ruthenium metal price has peaked early 2007 at 10 times its 2005 average selling price. The volatility and physical state also have a large CoO impact on the overall process, for instance via the process throughput, the need for high temperaturecompatible packaging and vaporisers, or the need of frequent on-board ampoule changes and resulting tool downtime for neat solids precursors.
Chemically speaking, suitable precursors that are being used in volume today are based on ligands given in the table 1 (or combination thereof), while the table 2 gives newer family of compounds. In the remainder of this section various considerations for the design of High-k and metal precursors will be discussed.
On the high-k side, and after the first generations with TAETO (Tantalum PentaEthOxide, Ta(OEt)5)) and TMA (Al2Me6), alkylamido compounds such as TEMAH, TEMAZ and TDMAH have taken the lead in the DRAM world, in combination with various alkylamino silanes, or TMA for the silicate and aluminates (or laminates) respectively. Due to the difficulty of substituting four large alkylamino groups on the silicon atom (steric hindrance effect) and higher volatility, partly substituted silanes with methyl or short alkyl chains are in general preferable for ALD deposition. ‘Small’ compounds like SAM.24, a Si-source designed by Air Liquide [Ref.5], bring higher volatility and better process performances in terms of uniformity at low dosage than the larger tetra-substituted silanes, allowing a tighter Si/Hf ratio control in high A/R structures.
Further improvements of Zr and Hf-based high k are driven by the need of extending the temperature window of pure ALD deposition to higher temperatures, as this yields denser films with lower impurities [Ref.6], and give a better control of the deposited oxide phase. Especially in Deep Trench DRAM technology, such precursors are almost mandatory to achieve pure ALD growth even at long exposure times. Recent general trend has consisted in switching from homoleptic precursor chemistry (such as TEMAH) to mixed ligand heteroleptic chemistry. In this later case, the most promising high stability candidates are based on metallocenes (i.e. cyclopentadienyl ‘Cp’ derivatives), either as ‘sandwich’ (= two Cp rings) molecules [Ref.7,8] or ‘half sandwich’ (= one Cp ring) such as the award winning MyALD family of precursors (Image 2) [Ref.9]. As opposed to the sandwich molecule (‘bis Cp’), the half sandwich, also referred to as “piano stools”, exhibit similar growth per cycle and vapour pressure as the common alkylamido compounds (see graph 1 for Hf), but at improved stability (see graph 2 for Zr, in which TEMAZ exhibits > 5% residue level despite being vaporised at the lowest temperature). Additionally the ‘half sandwich’ precursors are much simpler, and thus cheaper to synthesise than the sandwich molecules.
The incorporation of Rare Earth compounds in the next generation of memory devices places an even tougher challenge, as the ligand selection entices trade-offs between volatility, stability and melting point (MP). As a general rule, they exhibit much higher MP and lower volatility than Group IV compounds, which makes them tough to handle in deposition equipment. The usual ligands include 1. β-diketonates, 2. silylamides and more recently 3. cyclopentadienyl. As an example a comparison of the properties of Yttrium compounds is given in table 3.
1. As a general trend, β-diketonates are extremely thermally stable, have a very high MP, usually close to 200°C, and poor volatility. Ligand tailoring (in particular through ‘asymmetrisation’) allows reducing the MP to acceptable values, but ALD utilization also suffers from their poor reactivity to oxidising species (low growth per cycle, risk of carbonate formation) resulting in poor throughput.
2. Well known silylamides present high MP (also close to 200°C), poor thermal stability (decomposition usually below 250°C) but fairly acceptable volatility. Their main inherent drawback is uncontrolled Si incorporation, especially for O3 based processes.
3. The cyclopentadienyl family has recently attracted attention. Ln(RCp)3 compounds combine high thermal stability, low melting point and high reactivity toward oxidising species which results in ALD growth rates typically above 1Å/cycle. In addition, as for the β-diketonates, the Cp rings can be tailored by adding branching alkyl groups to fine-tune the precursor properties.
For the generation beyond, much considered materials are Alkaline Earths containing films such as STO and BST, containing elements as Strontium (Sr) and Barium (Ba). Alkaline Earth metal-organic chemistry raises even more challenges than the lanthanides series. As a general rule, volatility improvement is sought through the reduction of the molecularity (i.e. the number of molecules forming an independent ‘cluster’), which is usually high for Sr/Ba compounds. As an example, the standard strontium ‚-diketonate Sr(thd)2, is a trimer having a melting point of 215°C and a vapour pressure of ~0.1 Torr at 230°C. In addition, Alkaline earth β-diketonates present similarly low reactivity to oxidisers. Various routes such as mixed or/and bulkier ligand approach, adducts and solvatation are underway to improve the physical properties of the precursors, as exemplified by Air Liquide’s new Strontium precursor, HyperSr which has a melting point below 100°C and a vapour pressure of 2.5Torr at 200°C.
For gate oxides in CMOS manufacturing, the most promising chemistries today are either based on halides (for example hafnium tetrachloride) or on alkoxy derivatives such as Hafnium terbutoxide (HTB), sometimes in combination with a silicon source. The modification of the gate oxide compositions or the capping with new materials will most likely use the same family of rare earth precursors as currently under development for memories.
In DRAM devices, TiN electrodes deposited from TiCl4 or TDMAT are well entrenched and will prevail until other metals, most likely Ru are being incorporated. A vast catalogue of Ru compounds is under evaluation, often based on π-bonding with conjugated unsaturated hydrocarbons, either cyclic (branched cyclopentadienyls, or larger cycles) or linear. For the group with cyclic ligands, the most popular one being Ru(EtCp)2. However, stringent requirements to avoid columnar growth, enhance adhesion, limit incubation delay during deposition, and avoid O2 as necessary co-reactant, have led chemists to search for alternatives, often based on mixed ligands, as exemplified by Air Liquide’s CHORUS (Image 3).
For metal gate (non FUSI)
The continued scaling down of the gate dimensions of CMOS transistors lead to the emergence of major issues such as poly-silicon gate depletion, poly-silicon incompatibility with new gate dielectrics, boron diffusion into the dielectric and reduced reliability. Most of these issues may be reduced or eliminated by the use of a metal gate instead of the traditional poly-silicon gate. The major parameter to take into account is the work function, defined as the energy to extract an electron from the Fermi level to vacuum. nMOS material requires a work function as close as possible to 4.1 eV while pMOS needs a material with a value close to 5 eV.
Today, PVD, CVD and ALD are all studied in parallel. As opposed to what was initially anticipated, the integration of nMOS metals, considered as thermodynamically rather instable towards hafnium-based materials, were found to be rather easy to integrate. Conversely, metals suitable for pMOS channel, in principle difficult to oxidise and with no or limited interaction expected with the gate dielectrics, have a significantly lower work function at the interface with the high-k (where it is physically meaningful) compared to bulk values.
Among nMOS materials, hafnium and tantalum-based materials are the most promising candidates such as tantalum carbide and tantalum nitride. While sputtered films globally provided satisfaction, there is still no perfect solution for TaxC films in CVD. It is therefore expected that PVD will be preferred. For nitrides films, amido compounds are molecules of choice, especially TEMAH and/or TDMAH for HfCN and PDMAT or TBTDET for the stoichiometric metallic TaN. Some ternary nitrides such as TaAlN were even reported to reach the targeted work function, for which TDEAA (Al(NEt 2)3) seems suitable.
Silicon sources for spacers and stressors
Despite all the new elements that are entering the chip composition, the development of new silicon precursors remains essential to enable the new integration schemes. New silicon precursors such as HCDS (Si2Cl6), TSA ((SiH3)3N), aminosilanes or alkoxy silanols play a critical role to cope with the low thermal budget constraints for both silicon oxide and silicon nitride. In addition, many other silicon-based films are required throughout the FEOL.
As device scaling continues and semiconductor manufacturing truly enters the nanotechnology era, the incorporation of new elements is necessary to ensure the required improvements in device performance. Material engineers play an essential role in the development, synthesis and screening of new materials, to enable their rapid incorporation in IC production at acceptable costs.
In the design of precursors for the revolutionary ALD and CVD processes it is not only required to look at the pure material properties, but also to comply with a large number of process constraints like thermal budget, precursor delivery method. We have given an overview of the considerations when designing new precursors for metal and high-k applications. Similar design methods are applied when developing precursors for other applications like STI in Flash or BEOL metallisation.
 R.M. Wallace, ‘New Devices and Materials for 32nm and Beyond’, Semicon West 2007 TechXPOT conference
 K. Henson, M. Jurczak, ‘Metal-gate integration challenges’, Fabtech 25th Edition, February 2005
 R. DeJulie, ‘Silicides Support Advanced Gate Stacks’, Semiconductor International, Jan. 2007 edition.
 C. Dussarrat, I. Suzuki and K. Yanagita; ‘Extra Low-Temperature SiO2 Deposition Using Aminosilanes’, 210th ECS Meeting - Cancun, Mexico, October 2006.
 Ritala M. Leskela, M. In Handbook of Thin Film Materials; Nalwa, H. S., Ed. Academic Press: New York, 2002; 103-159.
 Putkonen M, Niinistö L, J. Mater. Chem, 2001, 11, 3141-3147
 Niinistö et al. ‘Atomic Layer Deposition of HfO2 Thin Films Exploiting Novel Cyclopentadienyl Precursors at High Temperatures’, Chem. Mater. 19 (13), 3319 -3324, 2007.
 Niinistö et al. To be published (Baltic ALD conference, September 17-21 2007)