Yield Management

Manufacturers of semiconductors used in the high-end computing (advanced microprocessors) and consumer (graphics and gaming chipsets) applications are using high-speed serial bus interfaces like PCI Express and HyperTransport to deliver data at rates up to 6.4 Gbps. According to the 2005 International Roadmap for Semiconductors (ITRS), 10 Gbps and above will be commonly used by the year 2010. And with industry experts now predicting data rates as high as 20 Gbps within ten years, some fundamental practices must change to enable the testing of these high-speed interfaces. This article explains how far-end loopback presents an innovative, cost-effective technology that can accelerate this important change, by effectively helping manufacturers to reduce the cost of test as well as cycle times of the next-generation semiconductors.

Design tools and manufacturing processes have improved to the point that the number of available logic gates no longer limits system-on-chip (SoC) performance. Instead, performance limits are dictated mostly by the speed at which data can be supplied to the device’s ‘core’ along with the management of power and heat. These factors are forcing fundamental changes in the way data is transferred into and out of the IC, which in turn impacts the complete spectrum of semiconductor production, from design to final test and packaging.

Previously, increasing the parallel bus width was considered the standard approach to use when moving larger volumes of data. Today, however, this approach is less effective as it ultimately increases power consumption and pin count, as well as raises packaging and PCB costs.Running an existing parallel bus faster has limitations, because of the inductive and capacitive properties of the interconnect layers. At wire data rates around 1 Gbps, the rise time, jitter, and inter-channel and distributed clock skew characteristics inherent in parallel bus designs start to reach critical limits.

These factors have convinced digital designers to seriously consider the serial techniques pioneered a decade ago by the data communications industry. For example, running very high data rates on a smaller number of serial channels in a PC architecture (Fig.1) enables both the data volume and power budget requirements to be met. High-speed serial buses (HSSB) have a number of physical features that distinguish them from parallel buses. Key differences include:
● Point-to-point connections vs. many-to-many connections on a traditional bus
● Fewer total connections for transmitting and receiving an equivalent amount of data
● Uni-directional signal paths vs. bi-directional signals
● SerDes with tracking receivers and CDR
● Lower voltage swings to support faster data transitions
● Radically different clocking and data capture schemes
● Differential signalling to overcome common-mode noise

High-speed Test Challenges
High-speed interfaces such as PCI Express I and II, HyperTransport 2.0 and 3.0, XAUI, XDR, RapidIO and InfiniBand are increasingly being used to deliver faster data rates (Fig.2.). Test companies will continue to play a critical role in delivering these exponentially higher speeds via HSSBs at notmuch-higher cost. However, faster serial buses introduce major test challenges - traditional functional test and simple design-fortest (DFT) methodologies no longer work. Older “functional” test flows on high-end automated test equipment (ATE) platforms can sometimes offer the most thorough test coverage, but these production-proven methods have the disadvantages of higher cost and test programming complexity. Moreover, cost per pin rises with bus speed in high-speed data applications, making traditional functional testing even less viable. Semiconductor manufacturers have thus turned to loopback techniques (i.e. using the device to source the test data and receive it back into the device for recognition) that enable comprehensive, cost optimised testing of today’s high-speed buses. There are several techniques in use today. The simplest take advantage of internal DUT loopback paths, a good test of at-speed functionality that unfortunately bypasses the I/O and therefore compromises overall test coverage. Another commonly employed loadboard loopback technique is called ‘near-end loopback’, a path on the loadboard between the transmit and receive ports of the device. This provides better test coverage but, as we will see, still has undesirable limitations. Far-end loopback techniques, such as that offered by the Sapphire D-6432DFT from Credence Systems, provide a comprehensive suite of test capabilities that optimise test coverage in a single insertion.

A simplified PCI Express (PCIe) lane is shown in Fig.3. Also indicated are various different possibilities for loopback locations, from purely internal loopback points that can be helpful at wafer probe, to loopback locations outside the device under test (DUT). While loopback testing is very effective, the manner in which it is implemented is especially critical, considering the typical loss budget for high-speed signals. This loss budget, which determines the magnitude of acceptable signal degradation, typically has three components—contributed by the transmitter, receiver, and interconnect, all of which could degrade the signal ‘eye’ and thus impact resultant test coverage.

Near-end loopback techniques have already introduced cost efficiencies in testing devices for high-end consumer/computing applications via ease of programming and reduced capital investment in ATE. Current near-end loopback (i.e. using the device to source the test data and receive it back into the device for recognition) techniques are simple and cost effective, but their inability to adequately address variables such as jitter, signal variations, and protocol performance lead to incomplete testing and test escapes. Near-end loopback techniques can be self-contained within the DUT with pathways created between the I/O pins. However, the inherent cost savings and simplicity come with tradeoffs in terms of coverage. These include no parametric measurements, a lack of signal control, and lower likelihood of catching faults related to signal integrity or bit errors. For example, a simple internal, or load board loopback, would allow a marginal receiver to ‘hide’ in the shadow of a robust transmitter and pass the loopback test screen.

Far-end Loopback Advantages
Between the two extremes, innovative techniques such as far-end loopback combine the flexibility of DFT with the more in-depth diagnostics of functional testing. Far-end loopback is being effectively implemented in new ATE system instruments like the Sapphire D-6432DFT from Credence Systems. The Sapphire D-6432DFT instrument is the first integrated test solution for highspeed serial buses to combine at-speed loopback testing with jitter measurement and injection, along with scan/functional and DC parametric test capabilities, all in a single insertion. Even more compelling is that it offers far-end loopback with programmable signal degradation (Fig.4.) which gives test engineers the flexibility of inserting the DUT DFT/pattern generator as far upstream as possible. Fig.4. shows a simple implementation on a single PCI Express lane with DUT master pattern generation at the core and the D-6432DFT instrument providing the far-end loopback. The end result is a much higher level of test coverage compared to the other loopback methods discussed.

The D-6432DFT delivers four times greater density than comparative offerings, presenting manufacturers with a breakthrough DFT methodology that dramatically lowers overall cost and timeto-market of today’s high-speed semiconductor devices. Unlike other approaches requiring investment in multiple instruments to test only a few lanes, the D-6432DFT integrates extensive functionality and enables testing of up to 16 loopback pairs on a single instrument. The new instrument was developed in partnership with microprocessor manufacturer Advanced Micro Devices (AMD), whose engineers are leveraging the Sapphire platform and the D-6432DFT to accelerate the time-to-test and time-to-market of their most advanced products. Over 200 D-6432DFT instruments are being used in production, building upon the Sapphire platform with an installed base of hundreds of testers worldwide.

Using the D-6432DFT, the DUT is placed in communication with an intelligent tester, making production-level testing of high-speed buses viable for the first time. The test engineer has the flexibility to program signal degradation for margining the transmit and receive channels of the device, along with being able to test for jitter tolerance and jitter transfer in a cost effective production environment.

This type of loopback offers significant advantages:
● Provides signal control to stress the eye in both the voltage and time domain
● Integrated jitter injection and jitter measurement
● Increased coverage in detecting sensitivity to signal integrity issues and bit errors
● Covers all three parts of the loss budget (transmitter, receiver, and interconnect)
● Receive and transmit channels can be used to deliver test vectors to the core logic and protocol stack
● Access to device pins for full DC parametric testing

It is important to remember that most devices have other signals, and even other buses that may conform to traditional interface standards. It is already common to find devices with several high-speed buses that are supported by different protocols and signalling specifications. In fact, it is the mix of technologies and time domains that make these devices so powerful and so vexing to design, debug, and test. Test companies can play an important leadership role in this fastpaced environment, by delivering innovative products and solutions that enable customers to optimise and accelerate their latest test methodologies at lower cost, while minimising risk.