Qimonda starts shipping DDR3
Qimonda optimized its new DDR3 SO-DIMM offerings for high power savings in an effort to lead the industry. Power efficiency is the key value proposition of the new DDR3 memory interface in mobile computing, as it allows for extended battery life at higher performance levels for notebooks and other mobile computing applications. This product introduction is a further important step in Qimonda`s DDR3 strategy and follows Qimonda's strong engagement in product definition, the early product introduction in June 2006 and the productive shipment start of DDR3 memories into Dektop PCs in May 2007.
"Qimonda's 1GB and 2GB SO-DIMMs enable customers to make full use of the significantly reduced power consumption and increased bandwidth of DDR3," said Michael Buckermann, Vice President of Business Unit Computing at Qimonda. "Qimonda is fully supporting its customers' launch of next-generation mobile computing applications, with DDR3 based notebooks expected to be introduced to the market in the first half of 2008."
The 1GB and 2GB SO-DIMM modules consist of 1Gbit DDR3 components manufactured by Qimonda in 75nm technology and offer a significant reduction in terms of power consumption, as they take full advantage of DDR3's 1.5V supply, compared to 1.8V with DDR2. By incorporating additional optimizations, DDR3 SO-DIMMs from Qimonda even reduce the power consumption by at least 30 and up to more than 50 percent compared to today's mainstream DDR2 modules, depending on the SO-DIMM capacity.
The Qimonda DDR3 SDRAM devices offer data transfer rates of up to 1.600 Mb/s (Mbit per second). This doubles the maximum data transfer rates of today's DDR2 memories, and significantly boosts the performance of PCs, mobile and server systems.
The DDR3 SO-DIMMs are based on DDR3 1Gbit components which have been jointly developed by Qimonda and its partner Nanya Technology Corporation. They support new functionality to permit its high processing speeds, such as Dynamic ODT (On Die Termination), which enhances signal integrity on the data bus required to run 2 DIMMs per channel at very high data rates. The Calibrated Driver Impedance optimizes the impedance of DDR3 SDRAM output drivers. In combination with reduced interface parasitics, read and write operations on the data bus make very high transfer rates possible.
