Berkeley Design Automation selected by Japanese supercomputer project
Berkeley Design Automation Inc., provider of circuit analysis technology for advanced analogue and RF integrated circuits (ICs), today announced that the company's Analogue FastSPICE circuit simulator has been selected for complex analogue and mixed signal block verification in a next generation 45nm supercomputer chip developed by the University of Tokyo and RIKEN.
“Berkeley Design Automation verification tools are critical to the success of our next generation 45nm supercomputer project,” said Professor Takashi Ikegami of the University of Tokyo. “Analogue FastSPICE delivered accuracy that is as good or better than traditional SPICE 5-10x faster on our complex analogue and mixed-signal blocks. Since we cannot rely on digital fastSPICE approximations for these designs, Analogue FastSPICE enables us to perform verification tasks that were previously impossible."
“Analogue FastSPICE is allowing us to verify our analogue and mixed-signal blocks faster than we thought possible,” said Duraid Madina, also of the University of Tokyo. “Analogue FastSPICE is not only faster and more accurate than our other SPICE tools, it is faster than digital fastSPICE tools that cannot handle our mixed signal designs. In our testing, Analogue FastSPICE was often 10x faster than the best traditional SPICE, while giving identical results. We never observed a difference greater than 0.15%.”
“We are delighted and honoured to be selected by the consortium as the circuit simulator of choice for the 45nm MDGRAPE-4 supercomputing chip,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “Our selection by this distinguished team is once again proof that Berkeley Design Automation’s Precision Circuit Analysis technology is essential for success in nanometre/RF design.”
