News Article
Synopsys and SMIC deliver enhanced 90-nm reference
Latest design flow streamlines development and testing of low power systems-on-a-chip. Reduced design and test costs.
Synopsys, a software company and IP for semiconductor design and manufacturing, and Semiconductor Manufacturing International Corporation (SMIC), a semiconductor foundry, announced the release of an enhanced 90 nm hierarchical, multi voltage RTL to GDSII reference design flow that benefits from advanced synthesis, design for test (DFT) and design for manufacturing (DFM) capabilities. Key features of the reference flow include topographical synthesis in the Design CompilerTM Ultra product, scan compression in the DFT MAX product and critical area analysis in the IC Compiler place and route product. Together these capabilities help to lower the cost of implementing and testing systems-on-a-chip (SoCs).
"We have worked closely with Synopsys to enhance our 90-nm reference flow. The latest iteration builds upon the previous flow's low power consumption, DFT and DFM capabilities," said Paul Ouyang, senior fellow of marketing and sales at SMIC. "The new flow reduces synthesis iterations and lowers test costs, providing our customers a path to significant cost savings and lower design risk."
The enhanced reference design flow 3.2, based on SMIC's 90 nm low leakage process and Synopsys' Pilot Design Environment, has been validated on Synopsys' Galaxy Design Platform with the ARM low power design kit developed for SMIC's 90 nm process. The reference flow uses Design Compiler Ultra topographical technology to accurately predict post layout timing, power and area during synthesis, thereby reducing costly design iterations between synthesis and layout. Advanced capabilities for low power design include insertion and placement optimisation of isolation cells, creation of multiple voltage areas and power meshes, and synthesis of multiple voltage aware clock trees. To help reduce standby leakage, the design flow utilises power gating techniques that shut off areas of the chip when they are not needed for a function. DFT MAX synthesises scan compression circuits that substantially lower costs by decreasing the amount of data and time required for manufacturing test. The tool reduces the number of scan chain connections that cross voltage domains, lowering the area impact of DFT by reducing the number of required level shifters and isolation cells. Other DFM capabilities in the flow include via optimisation and wire spreading and antenna fixing with Hercules runset."
"Our continued collaboration with SMIC allows us to work together to enhance the reference flow to meet our customers' changing needs in design for test, design for manufacturing and power management," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "Our work with SMIC enables us to provide the right advanced tools and techniques required by our joint customers to deliver first pass silicon success."
"We have worked closely with Synopsys to enhance our 90-nm reference flow. The latest iteration builds upon the previous flow's low power consumption, DFT and DFM capabilities," said Paul Ouyang, senior fellow of marketing and sales at SMIC. "The new flow reduces synthesis iterations and lowers test costs, providing our customers a path to significant cost savings and lower design risk."
The enhanced reference design flow 3.2, based on SMIC's 90 nm low leakage process and Synopsys' Pilot Design Environment, has been validated on Synopsys' Galaxy Design Platform with the ARM low power design kit developed for SMIC's 90 nm process. The reference flow uses Design Compiler Ultra topographical technology to accurately predict post layout timing, power and area during synthesis, thereby reducing costly design iterations between synthesis and layout. Advanced capabilities for low power design include insertion and placement optimisation of isolation cells, creation of multiple voltage areas and power meshes, and synthesis of multiple voltage aware clock trees. To help reduce standby leakage, the design flow utilises power gating techniques that shut off areas of the chip when they are not needed for a function. DFT MAX synthesises scan compression circuits that substantially lower costs by decreasing the amount of data and time required for manufacturing test. The tool reduces the number of scan chain connections that cross voltage domains, lowering the area impact of DFT by reducing the number of required level shifters and isolation cells. Other DFM capabilities in the flow include via optimisation and wire spreading and antenna fixing with Hercules runset."
"Our continued collaboration with SMIC allows us to work together to enhance the reference flow to meet our customers' changing needs in design for test, design for manufacturing and power management," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "Our work with SMIC enables us to provide the right advanced tools and techniques required by our joint customers to deliver first pass silicon success."
