Cadence acquires Chip Estimate
Cadence Design Systems, a provider of electronic design innovation, announced that it has acquired Chip Estimate Corporation, a provider of IC planning and enterprise level IP reuse management solutions. Founded in 2003, Chip Estimate products enable electronics design teams to predict the die size, yield, power consumption, performance, and cost of chips based on almost any design architecture, IP and silicon process node options.
In addition to its chip planning technology, Chip Estimate has developed the industry recognised portal, Chip Estimate's web site, which hosts a collaborative partnership of over 175 IP suppliers and foundries featuring over 6,000 IP components. The unique combination of Chip Estimate's IC prediction technology and chip planning portal enables customers to perform technical and cost benefit what-if analysis to drive cost optimised IC design and reduced project risk in a more efficient and reliable manner.
"We are excited to be combining our capabilities with an industry leader," said Adam Traidman, president and CEO of Chip Estimate. "Chip Estimate customers will benefit significantly from the synergies and opportunities created by the combination of the companies, and together we can deliver even greater value to the electronics design community."
"The Chip Estimate technology and Web portal are great complements to the Cadence solutions portfolio and fit perfectly with our strategy to partner with the design IP industry instead of compete with them," said Craig Johnson, corporate vice president, Marketing and Strategy at Cadence. "In addition to providing reliable ROI analysis to our customers, we will enable IC companies to improve their internal IP reuse productivity."
The acquisition was completed March 7. Terms of the agreement were not disclosed.
